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1. (WO2007011453) PIN ELECTRONICS DRIVER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/011453 International Application No.: PCT/US2006/020079
Publication Date: 25.01.2007 International Filing Date: 23.05.2006
Chapter 2 Demand Filed: 16.02.2007
IPC:
G01R 31/319 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
317
Testing of digital circuits
3181
Functional testing
319
Tester hardware, i.e. output processing circuits
Applicants:
TERADYNE, INC. [US/US]; 700 Riverpark Drive North Reading, MA 01864, US (AllExceptUS)
SARTSCHEV, Ronald A. [US/US]; US (UsOnly)
Inventors:
SARTSCHEV, Ronald A.; US
Agent:
PYSHER, Paul; Fish & Richardson P.C. 225 Franklin Street Boston, MA 02110-2804, US
Priority Data:
11/183,38218.07.2005US
Title (EN) PIN ELECTRONICS DRIVER
(FR) DISPOSITIF ELECTRONIQUE D'ENTRAINEMENT DE BROCHE
Abstract:
(EN) Circuitry for driving a pin includes a first resistive circuit connected to the pin, a first transistor circuit to connect the first resistive circuit to a logic level voltage in response to a trigger voltage, the first transistor circuit and the first resistive circuit together defining a termination impedance, and a driver circuit to apply the trigger voltage to the first transistor circuit. The driver circuit includes counterparts to the first resistive circuit and the first transistor circuit. The counterparts define a counterpart impedance that is controlled to control the trigger voltage and thereby control the termination impedance.
(FR) La présente invention se rapporte à un circuit permettant d'entraîner une broche, qui comprend un premier circuit résistant relié à la broche, un premier circuit à transistor destiné à connecter le premier circuit résistant à une tension de niveau logique en réponse à une tension de déclenchement, le premier circuit à transistor et le premier circuit résistant définissant ensemble une impédance terminale, et un circuit d'attaque destiné à appliquer la tension de déclenchement au premier circuit à transistor. Le circuit d'attaque comporte des homologues du premier circuit résistant et du premier circuit à transistor. Lesdits homologues définissent une impédance d'homologues qui est contrôlée, ce qui permet de réguler la tension de déclenchement, et donc de réguler l'impédance terminale.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080027349EP1904865JP2009501936CN101228452