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1. (WO2007011037) SEMICONDUCTOR MEMORY HAVING DATA ROTATION/INTERLEAVE FUNCTION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/011037    International Application No.:    PCT/JP2006/314522
Publication Date: 25.01.2007 International Filing Date: 21.07.2006
IPC:
G11C 16/06 (2006.01), G06F 12/06 (2006.01), G09G 5/24 (2006.01), G11C 11/413 (2006.01), G11C 16/02 (2006.01)
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP/JP]; 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501 (JP) (For All Designated States Except US).
KAWASHIMA, Keiji; (For US Only)
Inventors: KAWASHIMA, Keiji;
Agent: HAYASE, Kenichi; HAYASE & CO. Patent Attorneys, 4F The Sumitomo Building No. 2 4-7-28, Kitahama, Chuo-ku Osaka-shi, Osaka 5410041 (JP)
Priority Data:
2005-211520 21.07.2005 JP
Title (EN) SEMICONDUCTOR MEMORY HAVING DATA ROTATION/INTERLEAVE FUNCTION
(FR) MÉMOIRE SEMI-CONDUCTRICE COMPORTANT UNE FONCTION DE ROTATION/ENTRELACEMENT DES DONNÉES
(JA) データの回転またはインターリーブ機能を有する半導体メモリ装置
Abstract: front page image
(EN)A memory having a reduced scale and enabling processing reduction by reading predetermined bit data stored in memory addresses as a data output from the memory and memory applied device. The memory has multiplexers (301, ..., 3n-1n-2) for selectively outputting data in memory cells (000, ..., n-1m-1n-1) outputted by buffer circuits (200, ..., 2n-1n-1) one-bit by one-bit from each of memory cell arrays (10 to 1n-1) or n bits from one memory cell array.
(FR)Mémoire présentant une échelle réduite et permettant d'effectuer la réduction en lisant une donnée de bit prédéterminée enregistrée dans les adresses mémoire comme une donnée transmise de la mémoire et dispositif comportant la mémoire. La mémoire comporte des multiplexeurs (301, ..., 3n-1n-2) permettant de transmettre des données sélectivement vers des cellules mémoire (000, ..., n-1m-1n-1) transmises par des circuits tampons (200, ..., 2n-1n-1) un bit par un bit à partir de chaque matrice de cellule mémoire (10 à 1n-1) ou n bits depuis une matrice de cellules mémoire.
(JA) 複数のメモリアドレスに格納されている所定のビットデータを、メモリ装置からのデータ出力として読み出すことでメモリの削減と処理の負担を軽減することができるメモリ装置およびメモリ応用装置を提供することを目的とする。  本発明のメモリ装置は、バッファ回路(200,・・・,2n-1n-1)が出力するメモリセル(000,・・・,n-1m-1n-1)のデータを、各メモリセルアレイ(10)ないし(1n-1)から1ビットずつ、または1つのメモリセルアレイからnビットのいずれかを選択出力できるマルチプレクサ(301,・・・,3n-1n-2)を備える。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)