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1. (WO2007010793) SEMICONDUCTOR LIGHT-EMITTING DEVICE AND BOARD MOUNTED WITH SEMICONDUCTOR LIGHT EMITTING DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/010793 International Application No.: PCT/JP2006/313851
Publication Date: 25.01.2007 International Filing Date: 12.07.2006
IPC:
H01L 33/08 (2010.01) ,H01L 33/62 (2010.01) ,H01L 33/38 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
08
with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
62
Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
36
characterised by the electrodes
38
with a particular shape
Applicants:
松下電器産業株式会社 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP/JP]; 〒5718501 大阪府門真市大字門真1006番地 Osaka 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
東 和司 HIGASHI, Kazushi; null (UsOnly)
石谷 伸治 ISHITANI, Shinji; null (UsOnly)
Inventors:
東 和司 HIGASHI, Kazushi; null
石谷 伸治 ISHITANI, Shinji; null
Agent:
河宮 治 KAWAMIYA, Osamu; 〒5400001 大阪府大阪市中央区城見1丁目3番7号IMPビル 青山特許事務所 Osaka AOYAMA & PARTNERS IMP Building 3-7, Shiromi 1-chome Chuo-ku, Osaka-shi Osaka 540-0001, JP
Priority Data:
2005-20642115.07.2005JP
Title (EN) SEMICONDUCTOR LIGHT-EMITTING DEVICE AND BOARD MOUNTED WITH SEMICONDUCTOR LIGHT EMITTING DEVICE
(FR) DISPOSITIF ÉLECTROLUMINESCENT À SEMI-CONDUCTEUR ET CARTE ÉQUIPÉE DUDIT DISPOSITIF
(JA) 半導体発光素子及び半導体発光素子実装済み基板
Abstract:
(EN) A semiconductor light-emitting device has a plurality of bumps comprising a single n-bump formed on an n-electrode layer and multiple p-bumps formed on a p-electrode layer. The n-bump is disposed at the center of an array of the bumps where stress after mounting of the semiconductor light-emitting device may be produced with the lowest probability, thereby preventing joint failures after the mounting from occurring at the n-bump the number of which is smaller than that of the p-bumps. In a large-sized semiconductor light-emitting device, such a structure of the bump array can enhance the mounting reliability while improving the uniformity of the emission intensity.
(FR) La présente invention concerne un dispositif électroluminescent à semi-conducteur comprenant une pluralité de bosses et notamment une bosse n unique formée sur une couche d'électrode n et plusieurs bosses p formées sur une couche d'électrode p. La bosse n est disposée au centre d'un réseau formé par les bosses, à l'emplacement qui est le moins susceptible de subir une contrainte après le montage du dispositif électroluminescent à semi-conducteur. Ceci évite l'apparition de défaillances aux points d'épissure après le montage sur la bosse n, présente en nombre inférieur aux bosses p. Dans un dispositif électroluminescent à semi-conducteur de taille importante, ce type d'organisation du réseau de bosses accroît la fiabilité du montage tout en améliorant l'uniformité de l'intensité d'émission.
(JA)  n電極層上に形成された1個のnバンプと、p電極層上に形成された多数個のpバンプの複数個のバンプを配列させて備える半導体発光素子において、実装後の応力が最も生じ難いバンプ配列の中心にnバンプを配置することにより、pバンプに比してその個数が少ないnバンプにおける実装後の接合不良の発生を抑制することができる。このようなバンプ配列構成を採用することで、大型化された半導体発光素子において、発光強度の均一性を向上させながら、その実装における信頼性を高めることができる。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20100012965JP4680260CN101151740