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1. (WO2007010732) SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/010732 International Application No.: PCT/JP2006/313164
Publication Date: 25.01.2007 International Filing Date: 26.06.2006
IPC:
H01L 21/18 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/24 (2006.01) ,H01L 29/267 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
24
including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20 or H01L29/22246
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
26
including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24259
267
in different semiconductor regions
Applicants:
NISSAN MOTOR CO., LTD. [JP/JP]; 2, Takara-cho, Kanagawa-ku, Yokohama-shi, Kanagawa 2210023, JP (AllExceptUS)
YAMAGAMI, Shigeharu; null (UsOnly)
HOSHI, Masakatsu; null (UsOnly)
HAYASHI, Tetsuya; null (UsOnly)
TANAKA, Hideaki; null (UsOnly)
SHIMOIDA, Yoshio; null (UsOnly)
Inventors:
YAMAGAMI, Shigeharu; null
HOSHI, Masakatsu; null
HAYASHI, Tetsuya; null
TANAKA, Hideaki; null
SHIMOIDA, Yoshio; null
Agent:
MIYOSHI, Hidekazu ; Toranomon Kotohira Tower 2-8, Toranomon 1-chome Minato-ku, Tokyo 1050001, JP
Priority Data:
2005-20879819.07.2005JP
Title (EN) SEMICONDUCTOR DEVICE MANUFACTURING METHOD
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEURS
Abstract:
(EN) A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
(FR) La présente invention se rapporte à un procédé de fabrication d'un dispositif à semi-conducteurs possédant une couche de silicium polycristallin (5) qui comprend une étape de formation d'une couche de masque (7) sur la couche de silicium polycristallin (5), une étape de formation d'une paroi latérale (8) fournie sur une face latérale de la couche de masque (7) et qui couvre une partie de la couche de silicium polycristallin (6), une étape de dopage d'une impureté (52) dans la couche de silicium polycristallin (5) en utilisant au moins la couche de masque (7) ou la paroi latérale (8) comme masque et une étape de décapage de la couche de silicium polycristallin (5, 6) en utilisant au moins la couche de masque (7) ou la paroi latérale (8) comme masque.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080015947KR1020100068502EP1915773US20090233408CN101223629