Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2007010681) THIN FILM CAPACITOR AND METHOD FOR MANUFACTURING THIN FILM CAPACITOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/010681 International Application No.: PCT/JP2006/311306
Publication Date: 25.01.2007 International Filing Date: 06.06.2006
IPC:
H01G 4/33 (2006.01) ,H01G 4/12 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 23/12 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
33
Thin- or thick-film capacitors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
002
Details
018
Dielectrics
06
Solid dielectrics
08
Inorganic dielectrics
12
Ceramic dielectrics
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
株式会社 村田製作所 Murata Manufacturing Co., LTD. [JP/JP]; 〒6178555 京都府長岡京市東神足1丁目10番1号 Kyoto 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP (AllExceptUS)
竹島 裕 TAKESHIMA, Yutaka [JP/JP]; JP (UsOnly)
野村 雅信 NOMURA, Masanobu [JP/JP]; JP (UsOnly)
Inventors:
竹島 裕 TAKESHIMA, Yutaka; JP
野村 雅信 NOMURA, Masanobu; JP
Agent:
國弘 安俊 KUNIHIRO, Yasutoshi; 〒5320011 大阪府大阪市淀川区西中島5丁目14-10 カトキチ新大阪ビル10階 Osaka 10F, Katokichi shinosaka Bldg. 14-10, Nishinakajima 5-chome Yodogawa-ku, Osaka-shi Osaka 5320011, JP
Priority Data:
2005-20694315.07.2005JP
Title (EN) THIN FILM CAPACITOR AND METHOD FOR MANUFACTURING THIN FILM CAPACITOR
(FR) CONDENSATEUR À COUCHE MINCE ET PROCÉDÉ DE FABRICATION D’UN CONDENSATEUR À COUCHE MINCE
(JA) 薄膜キャパシタ及び該薄膜キャパシタの製造方法
Abstract:
(EN) Disclosed is a thin film capacitor comprising a capacitor unit formed on a substrate in which capacitor unit a first conductor layer and a second conductor layer are formed opposite to each other via a dielectric thin film; a first conductor pad which is electrically connected with one of the first and second conductor layers while being electrically insulated from the other conductor layer; a second conductor pad which is electrically insulated from the one conductor layer while being electrically connected with the other conductor layer; and first and second bumps respectively formed on the first conductor pad and the second conductor pad. In this thin film capacitor, the first and second conductor pads are joined to the substrate. By having such a constitution, even when a stress occurs in a bump in the vertical direction, the stress does not concentrate on a conductor.
(FR) La présente invention concerne un condensateur à couche mince comprenant une unité de condensateur placée sur un substrat dans laquelle unité une première couche conductrice et une seconde couche conductrice sont opposées l'une à l'autre de part et d'autre d'une couche mince de diélectrique ; une première pastille conductrice qui est électriquement connectée à l’une des première ou seconde couches conductrices tout en étant électriquement isolée de l’autre couche conductrice ; une seconde pastille conductrice qui est électriquement isolée de l’autre couche conductrice tout en étant électriquement connectée à l’autre couche conductrice ; et une première et une séconde bosse disposées respectivement sur la première pastille conductrice et sur la séconde pastille conductrice. Dans ce condensateur à couche mince, les première et seconde pastilles conductrices sont jointes au substrat. Une telle constitution permet que même si une contrainte se produit dans une bosse dans la direction verticale, la contrainte ne se concentre pas sur un conducteur.
(JA)  本発明の薄膜キャパシタは、第1の導体層と第2の導体層とが誘電体薄膜を介して対向状に形成されたキャパシタ部が、基板上に形成されると共に、前記第1の導体層及び前記第2の導体層のうちのいずれか一方の導体層と電気的に接続され、前記一方以外の他方の導体層と電気的に絶縁された第1の導体パッドと、前記一方の導体層と電気的に絶縁され、前記他方の導体層と電気的に接続された第2の導体パッドと、前記第1の導体パッド及び第2の導体パッド上にそれぞれに形成された第1及び第2のバンプとを備え、前記第1及び第2の導体パッドが前記基板に接合されている。これにより、バンプに鉛直方向の応力が生じた場合であっても、該応力が導体に集中しないようにした。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)