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1. (WO2007010660) WIRING BOARD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/010660 International Application No.: PCT/JP2006/309094
Publication Date: 25.01.2007 International Filing Date: 01.05.2006
IPC:
H01L 23/12 (2006.01) ,H01L 21/60 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 〒5458522 大阪府大阪市阿倍野区長池町22番22号 Osaka 22-22, Nagaike-cho, Abeno-ku, Osaka-shi Osaka 5458522, JP (AllExceptUS)
近間 義雅 CHIKAMA, Yoshimasa; null (UsOnly)
Inventors:
近間 義雅 CHIKAMA, Yoshimasa; null
Agent:
前田 弘 MAEDA, Hiroshi; 〒5410053 大阪府大阪市中央区本町2丁目5番7号 大阪丸紅ビル Osaka Osaka-Marubeni Bldg. 5-7, Hommachi 2-chome Chuo-ku, Osaka-shi Osaka 541-0053, JP
Priority Data:
2005-21024520.07.2005JP
Title (EN) WIRING BOARD
(FR) TABLEAU DE CÂBLAGE
(JA) 配線基板
Abstract:
(EN) Wiring comprises an upper wiring layer, a lower wiring layer, and an insulating film. The lower wiring layer is formed on the substrate side than the upper wiring layer. The insulating film is formed between the upper and lower wiring layers. The upper wiring layer includes a stress-applied area that receives a stress applied from a bump of an IC chip. The insulating film is formed in an area including at least the stress-applied area. The upper and lower wiring layers are connected with each other in an area, where the two wiring layers overlap each other in a plan view but the stress-applied area is excluded.
(FR) L'invention concerne un câblage qui comprend une couche de câblage supérieure, une couche de câblage inférieure et un film isolant. La couche de câblage inférieure est formée du même côté du substrat que la couche de câblage supérieure. Le film isolant est placé entre les couches de câblage supérieures et inférieures. La couche de câblage supérieure comprend une zone sur laquelle une tension est appliquée et qui reçoit une tension d'une protubérance d'une puce à circuits intégrés. Le film isolant est formé dans une zone comprenant au moins la zone recevant la tension. Les couches de câblage supérieures et inférieures sont reliées l'une à l'autre dans une zone où les deux couches de câblage se chevauchent dans une vue en plan mais la zone recevant la tension est exclue.
(JA) 【解決手段】  配線は、上層配線部と、上層配線部よりも基板側に形成された下層配線部と、上層配線部および下層配線部の間に形成された絶縁膜とを有する。上層配線部はICチップのバンプにより加圧を受ける被加圧領域を含む。絶縁膜は、前記被加圧領域を少なくとも含む領域に形成されている。上層配線部および下層配線部は、平面視において両配線部が重なる領域のうち前記被加圧領域を除く領域にて接続されている。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)