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1. (WO2007010600) SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/010600 International Application No.: PCT/JP2005/013294
Publication Date: 25.01.2007 International Filing Date: 20.07.2005
IPC:
H01L 29/78 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 27/092 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
Applicants:
富士通株式会社 FUJITSU LIMITED [JP/JP]; 〒2118588 神奈川県川崎市中原区上小田中4丁目1番1号 Kanagawa 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588, JP (AllExceptUS)
志渡 秀治 SHIDO, Hideharu [JP/JP]; JP (UsOnly)
三島 康由 MISHIMA, Yasuyoshi [JP/JP]; JP (UsOnly)
Inventors:
志渡 秀治 SHIDO, Hideharu; JP
三島 康由 MISHIMA, Yasuyoshi; JP
Agent:
國分 孝悦 KOKUBUN, Takayoshi; 〒1700013 東京都豊島区東池袋1丁目17番8号 池袋TGホーメストビル5階 Tokyo 5th Floor, Ikebukuro TG Homest Building 17-8, Higashi-Ikebukuro 1-chome Toshima-ku, Tokyo 1700013, JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) In the surface of an n-type element active region of a semiconductor substrate (1) having a (100) plane, generally rectangular grooves (4) are formed. The side perpendicular to the direction in which the grooves (4) extend is (110) plane. A gate insulating film (5) and a gate electrode (6) are formed on the surface of the semiconductor substrate (1) by thermal oxidation. The direction in which the gate electrode (6) extends is perpendicular to the direction ([1-10]) in which the grooves (4) extend. That is, the gate width direction is the [110] direction. A side wall insulating film (7) and a p-type source/drain diffusion layer (8) are formed.
(FR) La présente invention concerne la surface d'une région active d'élément de type n d’un substrat semi-conducteur (1) avec un plan (100), sur lequel sont formées des rainures généralement rectangulaires (4). Le côté perpendiculaire à la direction dans laquelle se prolongent les rainures (4) est plane (110). Un film d'isolation de grille (5) et une électrode de grille (6) sont formés sur la surface du substrat semi-conducteur (1) par oxydation thermique. La direction dans laquelle se prolonge l'électrode de grille (6) est perpendiculaire à la direction ([1-10]) dans laquelle s'étendent les rainures (4). En fait, la direction de la largeur de grille est la direction [110]. Un film d'isolement de la paroi latérale (7) et une couche de diffusion source/drain de type p (8) sont formés.
(JA)  表面が(100)面の半導体基板1のn型の素子活性領域の表面に、断面形状が実質的に矩形の複数の溝4を形成する。溝4の自身が延びる方向と直交する側面は、(1 1 0)面とする。続いて、熱酸化等により半導体基板1の表面にゲート絶縁膜5及びゲート電極6を形成する。このとき、ゲート電極6が延びる方向(ゲート幅方向)を、各溝4が延びる方向([1 -1 0]方向)に対して直交する方向とする。即ち、ゲート幅方向を[1 1 0]方向とする。次いで、サイドウォール絶縁膜7及びp型のソース/ドレイン拡散層8を形成する。
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)