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"Method for testing analog-to-digital converters "
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Field of the invention
The present invention relates to techniques for testing analog-to-digital converters.
The invention was developed paying particular attention to its possible application in the on-chip and/or on-board characterisation and/or testing of an analog-to-digital conversion device, particularly of the sigma-delta type, of the type that includes at least one input stage configured to perform an analog integration operation and at least one digital conversion stage.
By on-chip and on-board systems is meant systems that are situated on the same support, be it a chip or a card, as the analog-to-digital converter to be subjected to characterisation and/or testing.
Description of the known technology
Analog-to-digital converters (ADC) of the Sigma/Delta type are frequently used in consumer electronics systems, above all in the field relating to audio applications (recording/transmission of voice and music signals) where a resolution above 16 bit is required.
Therefore, being a component that is used in the consumer electronics market, it is fundamental that the cost of analog-to-digital converters be very low and their reliability very high. Testing operations must enable design specifications to be checked with a resolution in the order of -9OdB.
Since 60% of the cost of a mixed-signal circuit, such as the sigma-delta converter, depends on the design cost, which is normally amortised in production, 5-10% depends on packaging, and 35-30% on testing, this being a fixed component of the cost of the component, so that to reduce the latter would require a reduction of the cost of testing.
In particular, this problem is more strongly felt when the analog-to-digital converter presents high resolution, above 16 bit, as mentioned above. In this case it is extremely difficult to adopt low-cost testing and characterisation techniques with low systems impact. Indeed, it is necessary to generate analog waveforms with harmonic content below -9OdB (minimum) or -10OdB (optimal) . These waveforms can be generated with high-cost laboratory instruments and testing equipment, and data processing involves long testing times (above 3s) . This is not economic, since the duration of the test, which depends on the number of samples to be processed to evaluate the specifications with the desired accuracy, together with the measurement set-up cost, determines the cost of testing.
Testing and characterising the analog-to-digital converter directly on-chip or on-board is therefore to be preferred, provided that this does not increase the design cost of the device significantly (not above 10 eurocents) . Traditional techniques (of the analog and mixed-signal type) are however severely incompatible with the cost requirements indicated.
Furthermore, exhaustive testing, which entails the complete characterisation of the device and is performed with certified high-precision, and thus high-cost, instruments and is only feasible during the prototype phase, must be distinguished from production testing, during which only a sub-set of the device specifications can be verified. The cost of the component depends on the cost of production testing, and over recent years numerous researchers have been investigating ways to reduce test times during this phase, without however finding a solution that is univocally accepted by the scientific community.
The techniques at present most commonly used in the industrial field are:
Fourier discrete analysis, with consequent evaluation of parameters such as THD (Total Harmonic Distortion) , SNR (Signal-to-Noise Ratio) , gain, offset, on a large number of samples to achieve the required accuracy, to be combined with other techniques to complete the measurements (INL, DNL, power consumption, cross-talk) . A technique of this type is known, for example, from the publication by M. Toner and G. Roberts "A BIST scheme for an SNR test of a Sigma Delta ADC", International Test Conference, 1993;
the histogram technique, based on the statistical analysis of how many times each word of digital code occurs at the output of the ADC in the presence of an incoming ramp or sinusoid. This technique requires a large memory to be available and only tests the static characteristics of the device. An example of this technique may be found in the publication by A. Frisch & T. Almy, "HABIST: histogram-based analog built in self test", IEEE International Test Conference, ITC97, 3-5th Nov. 1997, Washington, DC, USA, pp. 760-767;
- servo-loop testing techniques based on reconfiguring the converter as an oscillator. In this case the specifications are not verified, but it is attempted to verify the absence of faults (fault driven test) . An example of this technique may be found in the publication by G. Huertas, D. Vazquez, E. Perelias, A. Rueda & J. L. Huertas, "Oscillation-based test in oversampling A/D converters", 7th IEEE International Mixed-Signal Testing Workshop, IMSTOl, 13-15th June 2001 Atlanta, GA, USA, pp.35-46;
- sine-wave curve fitting techniques based on reconstructing the waveform using a digital-to-analog converter. This, too, is a test of correct functioning, but does not evaluate the specifications. A technique of this type is known, for example, from the publication by M. J. Ohletz "Hybrid built in self-test

(HBIST) for mixed analogue/digital Ics" , 2nd European

Test Conference, ETC91, 10-12th April 1991, Munich, Germany, pp. 307-316;
the systematic testing of the digital subsystem alone, i.e. partial testing of the device;
- on-chip testing by generating synthetic analog signals on-chip and detecting the signals useful for testing on-chip.
All of the techniques mentioned above either do not test the specifications, as required in the industrial field, and/or are unable to operate adequately in the presence of a high-resolution converter. This is either because the number of samples required is very high, or because a waveform with too high a precision and with negligible harmonic content is required, difficult to obtain with low-cost instruments, let alone capable of on-chip implementation.
Recently, at the International Test Conference, a technique based on polynomial fitting was presented, and an example may be found In the publications by S. K. Sunter & N. Nagi, "A simplified polynomial-fitting algorithm for DAC and ADC BIST", IEEE International Test Conference, ITC97, 3-5th Nov. 1997, Washington, DC, USA, pp. 389-395 e A. Roy, S. Sunter, A. Fudoli & D. Appello, "High accuracy stimulus generation for A/D converter BIST", IEEE International Test Conference, ITC02, 8~10th Oct. 2002, Baltimore, MD, USA, pp. 1031- 1039". This technique uses, as test signal, an exponential step sequence. The method, which provides a marked reduction in testing time, can partially be implemented on-chip by using an FPGA (Field Programmable Gate Array) circuits both to generate and to process the signal.
However, the technique, which is proposed as a possible Built-in Self Test (BIST) for converters, presents limits due to the low resolution (-85dB) on the evaluation of specifications, and to its dependence on an analog filter, which cannot be implemented on-chip, to generate exponential wavefronts and that influences the accuracy of measurements.
Purpose of the invention and brief description
The present invention aims to solve the problem of providing a solution that enables analog-to-digital converters to be tested and/or characterised on-chip or on-board in a more efficient manner, with the required precision, exclusively using digital circuits and signals, through a digital circuit of very reduced complexity and without the addition of bulky analog components .
Furthermore, the invention has as its purpose that of providing a testing and/or characterisation method suitable to characterise the device both in production and in situ, and thus suitable for self-testing, and the further purpose of compensating for any non-linearity of the system with consequent reduction of the system's harmonic distortion.
According to the present invention, the goals outlined above are achieved thanks to a method having the characteristics related in the attached claims. The present invention also concerns a corresponding circuit, as well as a computer program product directly loadable into the memory of at least one computer, and including software code portions to perform said method when the product is run on said at least one electronic computer. As utilised here, reference to a computer program product is understood as being the equivalent of reference to a means readable by a computer containing instructions to control a computer-run system in order to co-ordinate performance of the method according to the invention. The reference to "at least one computer" points up the possibility that the present invention can be implemented in a distributed and/or modular manner.
In brief, the method described here entails generating a binary waveform, with calibrated levels, rectangular, of period coinciding with, or with a sub-multiple of, the sampling period, and with variable duty-cycle. The waveform thus generated is applied at the input of the analog-to-digital converter. This waveform executes, depending on the application, the function of test and/or characterisation waveform, such waveform constituting in general a digital characterisation signal.
The solution described here enables sigma/delta ADC converters (or equivalent) to be tested in their totality (that is, both the analog and the digital subsystems) with extremely high precision (at least to -95dB) , exclusively using digital circuits and signals, through a digital circuit of very reduced complexity and without the addition of bulky analog components. It also enables the device to be characterised both in production and in situ, and thus enables self-testing. Lastly, it enables any necessary compensation (both hardware and software) for non-linearity with consequent reduction of the system's harmonic distortion .
The method according to the invention is applicable to all analog-to-digital converters that, by their nature, have at their input an analog integrator such as, as a simple example, sigma/delta converters.
Brief description of the drawings
The invention will now be described, as a pure example without limiting intent, with reference to the figures in the attached drawings, in which:
- Figure 1 shows a diagram illustrating a signal used by the method subject of the invention;
- Figure 2 shows a diagram of the principle of a test circuit implementing the method according to the invention;
- Figure 3 shows a block diagram of an embodiment of a generator belonging to the test circuit in Figure 2;
- Figures 4a, 4b and Ac represent diagrams of signals generated in the generator in Figure 3.
Detailed description of embodiments of the invention given as examples
The proposed technique is based on the generation of a binary waveform, with calibrated levels, rectangular, of period coinciding with the sampling period, or a sub-multiple of that period, of the analog-to-digital converter and with variable duty cycle.
Figure 1 shows a time diagram that represents a sampling signal CLK, with period T, which is equal to the inverse of a sampling frequency F3. The same diagram, on the same time scale, shows a test waveform S according to the invention. In figure 1, η = —^-indicates the duty-cycle of that test waveform S, where Tx indicates the value of the half period of the test waveform S. VrefL and VrefH respectively indicate the minimum and the maximum reference levels of the analog- to-digital converter to be tested. The technique whereby the duty-cycle is varied is also known by the name PWM (Pulse Width Modulation) , but the levels of voltage, that is the reference levels VrefL and VrefH, are in this case analog and calibrated with regard to the specifications of the analog-to-digital converter to be tested.
The spectrum of such test waveform S lies well outside a band FSMAX that can be correctly sampled (according to the theorem of Nyquist this is equal to

F SVMUAΔXY = — 5 —L ) T and furthermore the test wavef orm
constitutes a signal of the binary type and of period exactly coincident with the sampling period T or with a sub-multiple of it. Nevertheless, the Applicant has observed that the presence of a stage that executes an analog integration at the input of the analog-to-digital converter means that the analog-to-digital conversion operation in reality sees and samples the integral of such test waveform S, that is a value Veq that corresponds to the area encompassed under the test waveform S. The value of the underlying area Veq is the-equivalent, for each sample i of the test waveform S, where i is an integer index, considered on the period of sampling T:
Veq =VrefL+(Vre/H-V,.φ)*φ-a)=V^+(V^-V^*(η(i)-a)
where η(i) = T{/T , since 0< ?7(0 <1 , indicates the duty-cycle of the ith sample and a is a constant correction factor, which takes into account the rise time and fall time of the binary signal.
Since the analog-to-digital converter has an input dynamic between the reference levels VrefL and VrefH, it acquires and converts to digital the duty-cycle of the ith sample η(i) , however adding to it the intrinsic errors ε(i) of the analog-to-digital converter (non-linearity, discretisation, harmonic distortion, etc. ) , that are under test/characterisation.
Thus by causing the duty-cycle of the ith sample η(i) to vary appropriately, it is obtained that the analog-to-digital converter converts to digital a value η(i) +a + ε(i) = f(η(i)) that is variable over time. With f ( . ) is indicated the characteristic of the analog-to-digital converter to be tested.
The proposed technique can thus be achieved, as a simple example, in two distinct forms:
according to a first embodiment an operation is provided for to generate a linear sequence η(i) = — , with N an integer that indicates the number of N
samples used for measurement, of variation of the duty-cycle of the test waveform S, and a subsequent operation of acquisition of an integer number N of consecutive output samples Q(i)=f{^(i))+ y, acquired at the output of the analog-to-digital converter, where f ( . ) is the characteristic of the converter that it is desired to measure, whereas Y is the analog-to~digital converter noise. By analysing the N samples of test waveform S generated with duty-cycle η(ϊ) ) , and by analysing the output samples ( q(i) } measured, through known techniques of polynomial regression, the best polynomial interpolator of the desired degree (usually third degree) a0 +atx+ a2x20x3 +n = f(x) is obtained, from which the parameters characterising the converter can be obtained (offset, gain, second and third harmonic distortion and noise} ;
-according to a second embodiment, an operation is provided for that generates a sinusoidal

sequence η(i)∞
of variation of the duty-cycle of the test waveform S (where the term of approximation is due to the necessary discretisation of the duty cycle) and acquires N consecutive output samples q(i)= f{v(i))+n, where f(.) is the characteristic of the converter to be measured, whereas γ is the analog-to-digital converter noise. The Fourier transform of the test waveform S generated (which is not spectrally pure, due to the discretisation of the duty-cycle, but its transform can in any case be calculated deterministically) may then be subtracted from the Fourier transform of the signal constituted by the output samples (<?(*)) acquired. The difference between the Fourier transforms {3(q(i))-Z(η(i)) ) represents the harmonic behaviour of the analog-to-digital converter.
From the standpoint of circuit implementation, the proposed method requires some digital circuits to generate the test waveform S of the PWM type.
Figure 2 shows a block diagram representing an analog-to-digital converter 10 associated to a test circuit 20 according to the invention. The test circuit 20 comprises a generator 21 to generate a modulated duty cycle signal S, that is sent directly to the analog input of the analog-to-digital converter 10. The test circuit 20 also includes an analysis circuit 22 that acquires and analyses the samples q{i) , leaving the analog-to-digital converter 10 and the samples η(i) applied at the input.
The circuit 20 is very simple, above all if the frequency dividers already present inside sigma/delta converters are exploited.
To produce the analysis circuit 22 to analyse the output samples q{ϊ) leaving the analog-to-digital converter 10 a few other circuits are also necessary to calculate the polynomial regressor and/or the Fourier transform. Considering the typical sampling frequency of sigma/delta converters, such circuits to calculate the polynomial regressor and/or the Fourier transform may be made, as a simple example, with serial bit techniques, that require a very limited number of logic gates. It should be noted that the complexity of these latter circuits may be reduced to negligible values, above all compared with the complexity of the decimator filter normally present at the output of an analog-to-digital converter 10, using serial bit calculation techniques. A simple analog multiplexer is also required, indicated with 30 in figure 2 and positioned between the output of the generator 21 and the input of the analog-to-digital converter 10, typically comprising two transmission gates, to generate a binary input signal with calibrated levels VrefL and VrefH, whose duty cycle is modulated according to the chosen PWM scheme. The dynamic parameters of the digital-to-analog converter thus measured may then easily be used for a post-processing, achieved through hardware on board the chip, or through software run by an external processor. Such post-processing may make it possible to reduce the equivalent harmonic distortion of the device .
Figure 3 shows a possible embodiment of the generator 21 of the test waveform. S.
Thus the generator 21 comprises a counter 211 that receives the sampling frequency F3 multiplied by a value 2n where n is the number of bits on which the counter 211 operates. This counter 211, that provides a count signal A, represented in the diagram in figure 4a, thus reaches its full-scale value 2n-l in a period equal to 1/F3. To obtain this counter 211, it is possible to exploit a counter that is already present inside many analog-to-digital converters on the market. Reference 212 indicates a sequence generator, that receives as Input frequency reference the sampling frequency Fs and generates an incremental sequence B, shown in the diagram in figure 4b, including duty-cycle values varied according to one of the two laws of variation described above, for example a linear sequence ?/(/) =— . Thus at each sampling period T equal
to 1/FS, corresponding to a sample i, a duty-cycle value η(i) is generated, until the top~of-scale value

2n-l is reached.
The count signal A and the Incremental sequence B are provided as input to a comparator 213, that checks whether the count signal A Is below the value of the Incremental sequence B and provides as test waveform S the result of this comparison operation. As may be understood in figure 4c, on each sampling period T=I/F3, the test waveform S has a high logic value as long as the value of the count signal A originated by the counter 211 is below the duty-cycle value η(i) set at that moment by the sequence generator 212 in the incremental sequence B, after which it passes to a low logic level when the count signal A goes above the duty-cycle value η{i) . Since the sequence generator 212 varies its output as a function of the chosen duty-cycle variation law, in this case η(J) = — , it follows that the test waveform S likewise has its own duty cycle modulated according to that law.
As has already been mentioned, a simple analog multiplexer, typically comprising two transmission gates, is sufficient to generate the incoming binary signal with the calibrated levels VrefL and VrefH, whose duty cycle is modulated according to the chosen PWM scheme .
The proposed technique has been verified through an experimental system on a commercial sigma/delta analog-to-digital converter {model PCM3002). The system consists of an analog-to-digital converter and a reprogrammable FPGA circuit assembled on the same card.
Thus the proposed method provides for the on-chip generation of a test/characterisation signal that, though it is digital, is sampled by the analog-to-digital converter exactly as a high-quality analog signal. This enables the outgoing signal from the converter to be generated and processed on-chip using simple digital circuits. To advantage this enables:
- self-testing and characterisation of the device both in a post-production phase and assembled in the definitive system;
- run-time compensation (and also compensation for varying environmental conditions) of non-idealities of the individual device, obtaining a device with better effective characteristics (i.e. higher quality) without increasing its price;
- if required, compensation for non-linearities of any external analog circuits (signal conditioning) , inserting them between the signal generator and the ADC converter;
- characterisation of the associated digital-to-analog converter (if present) .
Advantageously, the purely digital implementation of the technique also enables:
- effortless full on-chip integration, occupying a very small area;
- absence of analog components, whose presence could increase non-idealities and/or bulk and/or power consumption and/or require external components.
The method according to the invention finds application, for example, in testing sigma/delta converters in the audio sector and in particular in Codec. Further applications are in the field of interfacing with sensors. Characterisation of analog-to-digital converters may also be applied to the subsequent closed-loop characterisation of the digital-to-analog converter, usually associated to analog-to-digital converters.
Of course, without prejudice to the principle of the invention, , the construction details and embodiments may vary, also significantly, with regard to what is described and illustrated here, as a simple example without limiting intent, without thereby departing from the scope of the invention, as is defined in the annexed claims.
For example, the method according to the invention does not only apply to converters equipped with a purely analog input stage, but also to converters that implement the analog integration function in an equivalent manner, for example through switched capacitor circuits, or in any case through any circuit whose characteristics make them comparable to the characteristics of an integrator.
In the case of sinusoidal modulation of the duty cycle, it is clear that not only Fourier transform functions may be used, but any other spectral analysis function suited to the purpose such as Fast Fourier Transform, wavelet transform and similar functions.
According to an alternative embodiment of the proposed method, the polynomial regression may be calculated through a computer program product loadable into the memory of at least one computer (typically a microcontroller) that receives the digital samples in output from the analog-to-digital converter, while for the generator 21 a hardware embodiment is maintained. Naturally, the generator 21 may also the realised through a computer program product.
Note . that the digital characterisation signal is provided as input to the analog-to-digital converter, but it is not necessarily the case that the digital characterisation signal is sent directly to the input of the integrator; thus the presence of other circuits interposed between the digital characterisation signal and the integration stage, such as for example input protection systems, also falls under the sphere of protection of the solution described here, interposed circuits that however do not influence the parameters characterising the conversion operation, for the purposes of the method as described and claimed, or circuits for which such influence on the parameters characterising the conversion operation can be taken into account .