Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2007009846) CMOS TRANSISTORS WITH DUAL HIGH-K GATE DIELECTRIC AND METHODS OF MANUFACTURE THEREOF
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/009846 International Application No.: PCT/EP2006/063067
Publication Date: 25.01.2007 International Filing Date: 09.06.2006
IPC:
H01L 21/8234 (2006.01) ,H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants:
INFINEON TECHNOLOGIES AG [DE/DE]; St.-Martin-Str. 53 81669 München, DE (AllExceptUS)
LI, Hong-Jyh [--/US]; US (UsOnly)
Inventors:
LI, Hong-Jyh; US
Agent:
KINDERMANN, Peter ; Patentanwälte Kindermann Postfach 100234 85593 Baldham, DE
Priority Data:
11/187,19721.07.2005US
Title (EN) CMOS TRANSISTORS WITH DUAL HIGH-K GATE DIELECTRIC AND METHODS OF MANUFACTURE THEREOF
(FR) TRANSISTORS CMOS AVEC DIELECTRIQUE DE GRILLE A FORTE PERMITTIVITE DOUBLE ET LEURS PROCEDES DE FABRICATION
Abstract:
(EN) CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workplace having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V1 for the PMOS and NMOS FETs.
(FR) L'invention concerne des dispositifs CMOS dotés de transistors comprenant des matériaux diélectriques de grille différents ainsi que leurs procédés de fabrication. Un dispositif CMOS est formé sur une pièce à travailler comprenant une première zone et une seconde zone. Un premier matériau diélectrique de grille est déposé sur la seconde zone. Un premier matériau de grille est déposé sur le premier matériau diélectrique de grille. Un second matériau diélectrique de grille comprenant un matériau différent du premier matériau diélectrique de grille est déposé sur la première zone de la pièce à travailler. Un second matériau de grille est déposé sur le second matériau diélectrique de grille. Le premier matériau de grille, le premier matériau diélectrique de grille, le second matériau de grille et le second matériau diélectrique de grille sont soumis à une opération de formation de motifs en vue de l'obtention d'un dispositif CMOS présentant une valeur Vt symétrique pour les TEC PMOS et NMOS.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
DE112006001809