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1. (WO2007009024) FOLDED FRAME CARRIER FOR MOSFET BGA
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/009024 International Application No.: PCT/US2006/027167
Publication Date: 18.01.2007 International Filing Date: 12.07.2006
IPC:
H01L 21/50 (2006.01) ,H01L 21/48 (2006.01) ,H01L 21/44 (2006.01) ,H01L 23/495 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
44
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
Applicants:
FAIRCHILD SEMICONDUCTOR CORPORATION [US/US]; 82 RUNNING HILL ROAD MS: 35-4e South Portland, ME 04106, US (AllExceptUS)
MADRID, Ruben, P. [PH/PH]; PH (UsOnly)
GESTOLE, Marvin [PH/PH]; PH (UsOnly)
CRUZE, Erwin, Victor R. [PH/PH]; PH (UsOnly)
MANATAD, Romel, N. [PH/PH]; PH (UsOnly)
JAUD, Arniel [PH/PH]; PH (UsOnly)
CALO, Paul, Armand [PH/PH]; PH (UsOnly)
Inventors:
MADRID, Ruben, P.; PH
GESTOLE, Marvin; PH
CRUZE, Erwin, Victor R.; PH
MANATAD, Romel, N.; PH
JAUD, Arniel; PH
CALO, Paul, Armand; PH
Agent:
FITZGERALD, Thomas, R.; HISCOCK & BARCLAY, LLP 2000 HSBC Plaza Rochester, NY 14604-2404, US
Priority Data:
11/179,34812.07.2005US
Title (EN) FOLDED FRAME CARRIER FOR MOSFET BGA
(FR) SUPPORT DE CADRE REPLIE POUR GRILLE MATRICIELLE A BILLES (BGA) DE MOSFET
Abstract:
(EN) A folded frame carrier has a die attach pad (DAP) (30) and one or more folded edges (32, 33, 34, 35). Each folded edge has one or more studs (36) and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.
(FR) L'invention concerne un support de cadre replié comprenant une pastille de fixation de puce (DAP) (30) et un ou plusieurs bord(s) replié(s) (32, 33, 34, 35). Chaque bord replié comprend un ou plusieurs crampon(s) (36), chacun d'eux présentant une extrémité trapézoïdale. Le support de cadre replié est constitué de cuivre seul ou d'un alliage de cuivre. De multiples supports de cadre repliés peuvent être formés entre les rails opposés d'un cadre de montage. Les bords repliés sont coupés par une rainure en relief. Les pointes sont formées dans les bords de la DAP, puis repliées verticalement. Les pointes fournissent une connexion électrique avec le terminal sur la surface arrière d'un semi-conducteur de puissance monté sur la DAP.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080031270JP2009502026CN101553908