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1. (WO2007008682) GUARDRINGED SCR ESD PROTECTION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/008682 International Application No.: PCT/US2006/026549
Publication Date: 18.01.2007 International Filing Date: 10.07.2006
IPC:
H02H 3/00 (2006.01) ,H01L 23/62 (2006.01)
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
H
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
3
Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
62
Protection against overcurrent or overload, e.g. fuses, shunts
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. BOX 655474 Mail Station 3999 Dallas, TX 75265-5474, US (AllExceptUS)
STEINHOFF, Robert, Michael [US/US]; US (UsOnly)
Inventors:
STEINHOFF, Robert, Michael; US
Agent:
FRANZ, Warren, L. ; Texas Instruments Incorporated P.O. Box 655474, M/s 3999 Dallas, TX 75265-5474, US
Priority Data:
11/177,75508.07.2005US
Title (EN) GUARDRINGED SCR ESD PROTECTION
(FR) PROTECTION A ANNEAU DE GARDE SCR ESD
Abstract:
(EN) Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell (10). An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor (26) is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.
(FR) L'invention concerne des procédés et des circuits destinés à protéger un circuit électronique contre des endommagements ESD, au moyen d'une cellule SCR ESD (10). Un circuit SCR est couplé à un terminal d'un circuit microélectronique associé, pour lequel une protection ESD est désirable. Le SCR utilisé dans la cellule ESD selon l'invention est muni d'un anneau de garde complet pour protéger le SCR d'un déclenchement par des transitoires rapides. Il est prévu une résistance (26) sur l'anneau de garde, utilisable lors du déclenchement du SCR au début d'une situation ESD. Des formes d'exécution préférées de l'invention, fournies à titre d'exemple, sont données dans la description et ont trait à des résistances à blocs de siliciure, dans la gamme d'environ 2 1000 ohm ou moins.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1905141CN101258656