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1. (WO2007008579) SOURCE TRANSISTOR CONFIGURATIONS AND CONTROL METHODS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/008579 International Application No.: PCT/US2006/026317
Publication Date: 18.01.2007 International Filing Date: 06.07.2006
IPC:
H01L 29/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Applicants:
ZMOS TECHNOLOGY, INC. [US/US]; 1290 Oakmead Parkway, Suite 318 Sunnyvale, CA 94085, US (AllExceptUS)
YOO, Seung-Moon [KR/US]; US (UsOnly)
YOO, Jae, Hoon [KR/US]; US (UsOnly)
SOHN, Jeong Duk [KR/US]; US (UsOnly)
SON, Sung Ju [KR/US]; US (UsOnly)
CHOI, Myung Chan [KR/US]; US (UsOnly)
KIM, Young Tae [KR/US]; US (UsOnly)
YOON, Oh Sang [KR/US]; US (UsOnly)
HAN, San-Kyun [KR/US]; US (UsOnly)
Inventors:
YOO, Seung-Moon; US
YOO, Jae, Hoon; US
SOHN, Jeong Duk; US
SON, Sung Ju; US
CHOI, Myung Chan; US
KIM, Young Tae; US
YOON, Oh Sang; US
HAN, San-Kyun; US
Agent:
O'BANION, John P.; O'BANION & RITCHEY LLP 400 Capitol Mall, Suite 550 Sacramento, California 95814, US
Priority Data:
60/697,67208.07.2005US
Title (EN) SOURCE TRANSISTOR CONFIGURATIONS AND CONTROL METHODS
(FR) CONFIGURATIONS ET PROCEDES DE COMMANDE DE TRANSISTOR SOURCE
Abstract:
(EN) Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.
(FR) L'invention concerne des configurations de transistors sources, destinées à réduire le courant de fuite et les retards dans les circuits intégrés. Ces configurations permettent l'établissement d'une puissance virtuelle et de noeuds de mise à la masse au moyen d'un empilement de transistors, comprenant par exemple une superposition de deux transistors entre une première connexion d'alimentation virtuelle et VSS, et une seconde connexion d'alimentation virtuelle et VDD. Les commandes de grille de ces transistors superposés sont modulées par différents niveaux de tension en réponse à la puissance associée au mode de fonctionnement du circuit, tel que mode actif, mode veille-actif, et mode de non-consommation. L'invention concerne également des moyens permettant de commander ces empilements source. Dans une forme de réalisation, des noeuds virtuels distincts sont conçus pour différents types de circuits tels que tampons, RAS (impulsions de sélection de ligne), CAS (impulsions de sélection de colonne). D'autre techniques telles qu'une disposition directionnelle des transistors sont en outre décrites.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
DZDZP2007000816KR1020080034429EP1902471JP2009500959CN101228633