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1. (WO2007008326) MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/008326 International Application No.: PCT/US2006/022951
Publication Date: 18.01.2007 International Filing Date: 13.06.2006
IPC:
G11C 11/34 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
Applicants:
ATMEL CORPORATION [US/US]; 2325 Orchard Parkway San Jose, CA 95131, US (AllExceptUS)
TELECO, Nicola [IT/US]; US (UsOnly)
NGUYEN, Victor [US/US]; US (UsOnly)
Inventors:
TELECO, Nicola; US
NGUYEN, Victor; US
Agent:
SCHENEK, Thomas; SCHNECK & SCHNECK P.O. Box 2-E San Jose, CA 95109-0005, US
Priority Data:
11/178,96511.07.2005US
Title (EN) MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME
(FR) ARCHITECTURE DE MEMOIRE A SCHEMA AMELIORE DE PORTE DE COMMANDE TOLERANT UN ECRASEMENT
Abstract:
(EN) The present invention is related to semiconductor memories, and in particular to a nonvolatile or flash memory and method that reduces the effect of any over- erased memory cells in a memory array (301) . When a memory cell (Ml 231, M2 232) is read, a read voltage (306) is applied to the control gate (CGN) of at least one target memory cell, and a negative bias voltage (308) that is lower than a threshold voltage of an over-erased memory cell is also applied to the control gate (CGN-2, CGN+2, ...) of at least one other memory cell that is in the same row as the target memory cell . Applying a negative bias voltage to these other memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
(FR) L'invention concerne des mémoires semi-conductrices et, plus précisément, une mémoire non volatile ou flash et un procédé réduisant l'effet de cellules de mémoire écrasées quelconques dans un réseau mémoire (301). Quand une cellule de mémoire (Ml 231, M2 232) est lue, une tension de lecture (306) est appliquée à la porte de commande (CGN) d'au moins une cellule de mémoire cible et une tension de polarisation négative (308) inférieure à une tension seuil d'une cellule de mémoire écrasée est également appliquée à la porte de commande (CGN-2, CGN+2, ...) d'au moins une autre cellule de mémoire se trouvant dans la même rangée que la cellule de mémoire cible. L'application d'une tension de polarisation négative à ces autres cellules de mémoire éteint des cellules proximales, de manière à isoler le courant pouvant provenir des cellules de mémoire écrasées pendant une opération de lecture, de programme ou d'effacement.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1905043JP2009502001US20070008775CN101253572