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1. (WO2007008325) MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/008325 International Application No.: PCT/US2006/022946
Publication Date: 18.01.2007 International Filing Date: 13.06.2006
Chapter 2 Demand Filed: 27.04.2007
IPC:
G11C 8/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
Applicants:
ATMEL CORPORATION [US/US]; 2325 Orchard Parkway San Jose, CA 95131, US (AllExceptUS)
HONG, Stanley [US/US]; US (UsOnly)
WANG, Jami [US/US]; US (UsOnly)
CHEN, Alan [US/US]; US (UsOnly)
Inventors:
HONG, Stanley; US
WANG, Jami; US
CHEN, Alan; US
Agent:
SCHNECK, Thomas; SCHNECK & SCHNECK P.O. Box 2-E San Jose, CA 95109-0005, US
Priority Data:
11/179,24312.07.2005US
Title (EN) MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS
(FR) ARCHITECTURE DE MEMOIRE COMPRENANT DES CIRCUITS EVOLUES DE PARTITIONNEMENT DE LIGNES DE BITS PRINCIPALES POUR DES OPERATIONS D'EFFACEMENT/PROGRAMMATION/VERIFICATION AMELIOREES
Abstract:
(EN) The present invention provides a solution for long master bit lines (180a-180c) in a large capacity memory device (100) . A master bit line is partitioned by at least one switching transistor (181a-181i) placed on the master bit line.
(FR) La présente invention apporte une solution aux problèmes liés aux longues lignes de bits principales (180a-180c) dans un dispositif mémoire de grande capacité (100). Selon l'invention, une ligne de bits principale est partitionnée par au moins un transistor de commutation (181a-181i) placé sur la ligne de bits principale.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1905042JP2009507315CN101243517