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1. (WO2007008324) HIGH-SPEED INTERFACE FOR HIGH-DENSITY FLASH WITH TWO LEVELS OF PIPELINED CACHE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/008324 International Application No.: PCT/US2006/022945
Publication Date: 18.01.2007 International Filing Date: 13.06.2006
IPC:
H01L 27/115 (2006.01) ,G06F 13/00 (2006.01) ,G06F 3/00 (2006.01) ,G06F 7/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
Applicants:
ATMEL CORPORATION [US/US]; 2325 Orchard Parkway San Jose, CA 95131, US (AllExceptUS)
ADUSUMILLI, Vijay, P. [IN/US]; US (UsOnly)
Inventors:
ADUSUMILLI, Vijay, P.; US
Agent:
SCHNECK, Thomas; SCHNECK & SCHNECK P.o. Box 2-e San Jose, CA 95109-0005, US
Priority Data:
11/178,71311.07.2005US
Title (EN) HIGH-SPEED INTERFACE FOR HIGH-DENSITY FLASH WITH TWO LEVELS OF PIPELINED CACHE
(FR) INTERFACE HAUTE VITESSE POUR MEMOIRE FLASH HAUTE DENSITE PRESENTANT DEUX NIVEAUX DE CACHE PIPELINE
Abstract:
(EN) A memory circuit (100) and a method (500) of operating a flash or EEPROM device that has two levels (31, 32) of internal cache. A memory device having a memory array (10) , sense amplifiers (11) , a data register (20) , cache (30) , an input-output circuit (40) , and a control logic circuit (50) is configured to output data while simultaneously reading data from the memory array to the data register or simultaneously copying data from the data register to a first level (31) of internal cache. In addition, the memory device is configured to output data while simultaneously writing data from the data register to the memory array.
(FR) L'invention concerne un circuit de mémoire (100) et un procédé (500) pour faire fonctionner une mémoire flash ou EEPROM présentant deux niveaux (31, 32) de cache interne. L'invention concerne notamment un dispositif mémoire comprenant une matrice mémoire (10), des amplificateurs de détection (11), un registre de données (20), un cache (30), un circuit d'entrée-sortie (40) et un circuit logique de commande (50), ce dispositif étant conçu pour sortir des données simultanément à la lecture de données de la matrice mémoire au registre de données ou simultanément à la copie de données du registre de données vers un premier niveau (31) de cache interne. Par ailleurs, ce dispositif mémoire est conçu pour sortir des données simultanément à l'écriture de données du registre de données vers la matrice mémoire.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)