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1. (WO2007008178) HIGH PERFORMANCE COMPUTER ARCHITECTURE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/008178 International Application No.: PCT/SG2006/000194
Publication Date: 18.01.2007 International Filing Date: 12.07.2006
Chapter 2 Demand Filed: 12.02.2007
IPC:
G06F 15/17 (2006.01) ,G06F 11/20 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
16
Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
163
Interprocessor communication
17
using an input/output type connection, e.g. channel, I/O port
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
16
Error detection or correction of the data by redundancy in hardware
20
using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Applicants:
CONTINUUM SCIENCE AND TECHNOLOGIES SDN BHD [MY/MY]; 31-3, Metro Center, Jalan 8/146 Bandar Tasik Selatan 57000 Kuala Lumpur, MY (AllExceptUS)
NG, Liang Shing [MY/MY]; MY (UsOnly)
Inventors:
NG, Liang Shing; MY
Agent:
CHOW, Weng Weng; No. 151, Chin Swee Road #09-11/13, Manhattan House Singapore 169876, SG
Priority Data:
PI 2005321714.07.2005MY
Title (EN) HIGH PERFORMANCE COMPUTER ARCHITECTURE
(FR) ARCHITECTURE INFORMATIQUE HAUTE PERFORMANCE
Abstract:
(EN) Architecture for high performance computing comprises arrays of processor-memory chip (13) containing arrays of processor-memory cell (14). Each processor-memory cell has a processing unit (16) and a local memory (15). The arrays of processor-memory chips can be connected to other arrays through a common motherboard or by other networking means. Processing power is increased through the presence of a higher number of processing units and the direct connection of memory units to corresponding processor units reducing data transmission bottlenecks. Processor-memory cells can also be bypassed if found defective allowing processor-memory chips with faulty processor-memory cells to be considered acceptable for use.
(FR) La présente invention concerne une architecture pour calcul haute performance comprenant des réseaux de puces de processeur-mémoire (13) contenant des réseaux de cellules de processeur-mémoire (14). Chaque cellule de processeur-mémoire comporte une unité de traitement (16) et une mémoire locale (15). Les réseaux de puces de processeur-mémoire peuvent être connectés à d’autres réseaux par le biais d’une carte-mère commune ou par d’autres moyens de réseau. La puissance de traitement est accrue par la présence d’un nombre supérieur d’unités de traitement et la connexion directe des unités de mémoire à des unités de processeur correspondantes, ce qui réduit les embouteillages de transmission de données. Les cellules de processeur-mémoire peuvent être également dérivées si elles se révèlent défaillantes, ce qui permet à des puces de processeur-mémoire ayant des cellules de processeur-mémoire défaillantes de pouvoir être considérées aptes à être utilisées.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)