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1. (WO2007007861) MULTILAYER PRINTED WIRING BOARD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/007861 International Application No.: PCT/JP2006/314015
Publication Date: 18.01.2007 International Filing Date: 07.07.2006
IPC:
H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
イビデン株式会社 IBIDEN CO., LTD. [JP/JP]; 〒5038604 岐阜県大垣市神田町2丁目1番地 Gifu 1, Kanda-cho 2-chome, Ogaki-shi, Gifu 5038604, JP (AllExceptUS)
高橋 通昌 TAKAHASHI, Michimasa [JP/JP]; JP (UsOnly)
三門 幸信 MIKADO, Yukinobu [JP/JP]; JP (UsOnly)
中村 武信 NAKAMURA, Takenobu [JP/JP]; JP (UsOnly)
青山 雅一 AOYAMA, Masakazu [JP/JP]; JP (UsOnly)
Inventors:
高橋 通昌 TAKAHASHI, Michimasa; JP
三門 幸信 MIKADO, Yukinobu; JP
中村 武信 NAKAMURA, Takenobu; JP
青山 雅一 AOYAMA, Masakazu; JP
Agent:
小川 順三 OGAWA, Junzo; 〒1040061 東京都中央区銀座2丁目8番9号 木挽館銀座ビル Tokyo Kobikikan Ginza Bldg. 8-9, Ginza 2-chome Chuo-ku Tokyo 1040061, JP
Priority Data:
2005-19944207.07.2005JP
Title (EN) MULTILAYER PRINTED WIRING BOARD
(FR) CARTE DE CIRCUIT IMPRIMÉ MULTICOUCHE
(JA) 多層プリント配線板
Abstract:
(EN) In a multilayer printed wiring board, insulating layers and conductor layers are alternately stacked, and the conductor layers are electrically connected through via holes arranged on the insulating layers. The via hole is formed to have a swell at least on a part of it, in a substantially vertical direction to a thickness direction of the insulating layer. External stresses, such as a force of impact when dropped, are suppressed to have an insulating substrate not to easily warp, and cracks, disconnection, and the like of the conductor circuit are prevented. Thus, deterioration of reliability and drop impact resistance of a mounting substrate can be reduced.
(FR) La présente invention concerne une carte de circuit imprimé multicouche présentant une structure qui superpose successivement des couches isolantes et des couches conductrices, ces dernières étant connectées électriquement via des trous de raccordement disposés sur les couches isolantes. Le trou de raccordement est formé pour présenter au moins partiellement un ventre, dans une direction sensiblement verticale vers un sens d’épaisseur de la couche isolante. Des contraintes externes, telles qu’une force d’impact en cas de chute, sont éliminées pour obtenir un substrat isolant qui résiste à la torsion, et la craquelure, la déconnexion ou une action similaire du circuit conducteur sont évitées. On peut ainsi réduire une perte de fiabilité et de résistance au choc de chute d’un substrat de montage.
(JA) 絶縁層と導体層とが交互に積層され、導体層同士が絶縁層に設けたバイアホールを介して電気的に接続されてなる多層プリント配線板は、そのバイアホールは、少なくともその一部において、絶縁層の厚み方向に対してほぼ垂直な方向に膨らみを有して形成され、落下した際の衝撃力等の外部応力を抑制して、絶縁基板が反りにくくして、導体回路のクラックや、断線等を防止し、実装基板の信頼性や耐落下性の低下を軽減することができる。
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
KR1020070070224EP1858308JPWO2007007861US20070154741US20090255111US20100155130
CN101069457JP4913053IN1279/KOLNP/2007