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1. (WO2007006764) METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/006764 International Application No.: PCT/EP2006/064035
Publication Date: 18.01.2007 International Filing Date: 07.07.2006
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/423 (2006.01) ,H01L 29/51 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
51
Insulating materials associated therewith
Applicants:
STMICROELECTRONICS S.r.l. [IT/IT]; Via C. Olivetti, 2 I-20041 Agrate Brianza, IT (AllExceptUS)
ARENA, Giuseppe [IT/IT]; IT (UsOnly)
DONATO, Caterina [IT/IT]; IT (UsOnly)
CAMALLERI, Cateno Marco [IT/IT]; IT (UsOnly)
MAGRI', Angelo [IT/IT]; IT (UsOnly)
Inventors:
ARENA, Giuseppe; IT
DONATO, Caterina; IT
CAMALLERI, Cateno Marco; IT
MAGRI', Angelo; IT
Agent:
JORIO, Paolo ; Studio Torta S.r.l. Via Viotti, 9 I-10121 Torino, IT
Priority Data:
05425483.408.07.2005EP
Title (EN) METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE
(FR) PROCEDE DE FABRICATION DE DISPOSITIF D'ALIMENTATION A SEMI-CONDUCTEURS A GRILLE ISOLEE FORMEE DANS UNE TRANCHEE
Abstract:
(EN) A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).
(FR) Formation de tranchée (5) dans un corps à semi-conducteurs (2) : les parois latérales et le fond de la tranchée sont recouverts d'une première couche de matériau diélectrique (9); la tranchée (5) est remplie d'une seconde couche de matériau diélectrique (10); les deux couches (9, 10) sont attaquées selon une attaque partielle, simultanée et contrôlée, de sorte que les matériaux diélectriques aient un degré d'attaque similaire; une couche d'oxyde de grille (13) d'épaisseur inférieure à celle de la première couche susmentionnée (9) est déposée sur les parois de la tranchée (5); une région de grille (14) en matériau conducteur est formée dans la tranchée (5); et des régions de corps (7) et des régions de source (8) sont formées dans le corps à semi-conducteurs (2), sur les côtés de la région isolée et en isolation par rapport à elle (14). Ainsi, la région de grille (14) s'étend seulement au sommet des parties restantes des deux premières couches susmentionnées (9, 10).
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20080211015CN101258588