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1. (WO2007006508) METHOD FOR REALISING AN ELECTRIC LINKAGE IN A SEMICONDUCTOR ELECTRONIC DEVICE BETWEEN A NANOMETRIC CIRCUIT ARCHITECTURE AND STANDARD ELECTRONIC COMPONENTS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/006508 International Application No.: PCT/EP2006/006676
Publication Date: 18.01.2007 International Filing Date: 07.07.2006
IPC:
B82B 3/00 (2006.01) ,G11C 13/02 (2006.01) ,H01L 21/768 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
82
NANO-TECHNOLOGY
B
NANO-STRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
3
Manufacture or treatment of nano-structures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
13
Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
02
using elements whose operation depends upon chemical change
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
STMICROELETRONICS S.R.L. [IT/IT]; Via C. Olivetti, 2 I-20041 Agrate Brianza, IT (AllExceptUS)
MASCOLO, Danilo [IT/IT]; IT (UsOnly)
CEROFOLINI, Gianfranco [IT/IT]; IT (UsOnly)
Inventors:
MASCOLO, Danilo; IT
CEROFOLINI, Gianfranco; IT
Agent:
BOTTI, Mario ; Botti & Ferrari S.r.l. Via Locatelli, 5 I-20124 Milano, IT
Priority Data:
05425488.308.07.2005EP
Title (EN) METHOD FOR REALISING AN ELECTRIC LINKAGE IN A SEMICONDUCTOR ELECTRONIC DEVICE BETWEEN A NANOMETRIC CIRCUIT ARCHITECTURE AND STANDARD ELECTRONIC COMPONENTS
(FR) PROCEDE PERMETTANT DE REALISER UNE LIAISON ELECTRIQUE DANS UN DISPOSITIF ELECTRONIQUE SEMI-CONDUCTEUR ENTRE UNE STRUCTURE DE CIRCUIT NANOMETRIQUE ET DES COMPOSANTS ELECTRONIQUES STANDARDS
Abstract:
(EN) The present invention relates to a method for realising an electric connection in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components, which comprising the steps of: a) providing a nanometric circuit architecture comprising a succession (array) (3) of conductive nanowires (2) being substantially parallel to each other and extended along a predetermined direction x; b) realising, above the succession (3) of nanowires (2), an insulating layer (6); c) opening, on the insulating layer (6), a window (7) of nanometric width b extended along a direction inclined of an angle &agr; with respect to the extension direction x of the nanowires (2) so as to substantially cross the whole succession (3) of nanowires (2), with exposure of a succession (11) of exposed portions (10) of the nanowires (2), one for each nanowire; d) realising, above the insulating layer (6), a plurality of conductive dies (4) extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies (4) overlapping in correspondence with said window (7) onto a respective exposed portion (10) of a nanowire (2) with obtainment of a plurality of contacts (5) realising said electric connection.
(FR) Cette invention concerne un procédé permettant de réaliser une connexion électrique dans un dispositif électronique semi-conducteur entre une structure de circuit nanométrique et des composants électroniques standards, lequel procédé comprend les étapes consistant: a) à utiliser une structure de circuit nanométrique comprenant une succession (réseau) (3) de nanofils conducteurs (2) substantiellement parallèles les uns aux autres et s'étendant dans une direction x prédéterminée; b) à réaliser, au-dessus de la succession (3) de nanofils (2), une couche isolante (6); c) à ouvrir, sur la couche isolante (6), une fenêtre (7) de largeur nanométrique b s'étendant dans une direction inclinée d'un angle $g(a) par rapport à la direction d'extension x des nanofils (2) de façon qu'elle croise substantiellement toute la succession (3) de nanofils (2), avec exposition d'une succession (11) de parties exposées (10) des nanofils (2), une pour chaque nanofil; d) à réaliser, au-dessus de la couche d'isolation (6), une pluralité de matrices conductrices (4) s'étendant dans une direction y substantiellement orthogonale par rapport à la direction x et orientées face aux composants électroniques standards, chacune de ces matrices (4) chevauchant, en correspondance avec la fenêtre (7), une partie exposée correspondante (10) d'un nanofil (2) avec obtention d'une pluralité de contacts (5) réalisant la connexion électrique.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN101218169