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1. (WO2007005870) POWER INTERCONNECT STRUCTURE FOR BALANCED BITLINE CAPACITANCE IN A MEMORY ARRAY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005870 International Application No.: PCT/US2006/026041
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
IPC:
H01L 23/522 (2006.01) ,H01L 23/528 (2006.01) ,H01L 27/105 (2006.01) ,H01L 21/8239 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
Applicants:
SPANSION LLC [US/US]; 915 DEGUIGNE DRIVE MAIL STOP 250 P.o. Box 3453 Sunnyvale, CA 94088-3453, US (AllExceptUS)
AKAOGI, Takao [JP/US]; US (UsOnly)
Inventors:
AKAOGI, Takao; US
Agent:
JAIPERSHAD, Rajendra; ONE AMD PLACE Mail Stop 68, P.o. Box 3453 Sunnyvale, CA 94088-3453, US
Priority Data:
11/173,93001.07.2005US
Title (EN) POWER INTERCONNECT STRUCTURE FOR BALANCED BITLINE CAPACITANCE IN A MEMORY ARRAY
(FR) STRUCTURE D'INTERCONNEXION D'ALIMENTATION POUR CAPACITE DE LIGNES DE BITS EQUILIBREE DANS UNE MATRICE MEMOIRE
Abstract:
(EN) According to one exemplary embodiment, a semiconductor die includes a memory core array (302) situated over a substrate, where the memory core array (302) includes a number of bitlines (306a,306b,306c), where the bitlines (306a,306b,306c) can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure (307) situated over the memory core array (302), where the interconnect structure (307) is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines (306a,306b,306c). The interconnect structure (307) can include at least one interconnect line (310,312), which can form an angle (318) with respect to the bitlines (306a,306b,306c) that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure (307) can form one of a number of capacitances with each of the bitlines (306a,306b,306c), where each of the capacitances can be substantially equal in value to each other of the capacitances.
(FR) Selon un mode de réalisation, une puce semi-conductrice comprend une matrice noyau de mémoire (302) située sur un substrat, la matrice noyau de mémoire (302) comprenant un certain nombre de lignes de bits (306a, 306b, 306c), les lignes de bits (306a, 306b, 306c) pouvant être situées dans une première couche métallique d'interconnexion de la puce semi-conductrice. La puce semi-conductrice comprend également une structure d'interconnexion (307) située sur la matrice noyau de mémoire (302), la structure d'interconnexion (307) étant située dans une seconde couche métallique d'interconnexion de la puce semi-conductrice et située sur chacune des lignes de bits (306a, 306b, 306c). La structure d'interconnexion (307) peut comprendre au moins une ligne d'interconnexion (310, 312), laquelle peut former un angle (318) par rapport aux lignes de bits (306a, 306b, 306c) qui peut être supérieur à 0,0 degrés et inférieur ou égal à 90,0 degrés. La structure d'interconnexion (307) peut former une capacité d'un certain nombre de capacités avec chacune des lignes de bits (306a, 306b, 306c), chacune des capacités pouvant être sensiblement égale en valeur à l'une ou l'autre des capacités.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1905082