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1. WO2007005862 - SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER AND ASSOCIATED METHODS

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THAT WHICH IS CLAIMED IS:
1. A semiconductor device comprising:
a substrate;
an insulating layer on said substrate;
a semiconductor layer on said insulating layer on a side thereof opposite said substrate; and
a superlattice on said semiconductor layer on a side thereof opposite said insulating layer;
said superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions .
2. The semiconductor device of Claim 1 wherein said semiconductor layer and said base
semiconductor monolayers each comprises a same
semiconductor material .
3. The semiconductor device of Claim 1 wherein said substrate, said semiconductor layer and said base semiconductor monolayers each comprises silicon; and wherein said insulating layer comprises silicon oxide.
4. The semiconductor device of Claim 1 wherein said semiconductor layer has a thickness of less than about 10 nm.
5. The semiconductor device of Claim 1 further comprising:
spaced-apart source and drain regions laterally adjacent said superlattice to define a channel therein;

a gate dielectric layer overlying said
superlattice; and
a gate electrode layer overlying said gate dielectric layer.
6. The semiconductor device of Claim 5 further comprising a contact layer on at least one of said source and drain regions .
7. The semiconductor device of Claim 1 wherein each non-semiconductor layer is a single
monolayer thick.
8. The semiconductor device of Claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
9. The semiconductor device of Claim 1 wherein the superlattice further comprises a base
semiconductor cap layer on an uppermost group of layers.
10. The semiconductor device of Claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
11. The semiconductor device of Claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
12. The semiconductor device of Claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.
13. The semiconductor device of Claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

14. The semiconductor device of Claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
15. The semiconductor device of Claim 1 wherein opposing base semiconductor portions in adjacent groups of layers are chemically bound together.
16. A method for making a semiconductor device comprising:
forming an insulating layer on a substrate;
forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate; and
forming a superlattice on the semiconductor layer on a side thereof opposite the insulating layer;
the superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions .
17. The method of Claim 16 wherein the
semiconductor layer and the base semiconductor monolayers each comprises a same semiconductor material .
18. The method of Claim 16 wherein the
substrate, the semiconductor layer and the base
semiconductor monolayers each comprises silicon; and wherein the insulating layer comprises silicon oxide.

19. The method of Claim 16 wherein the
semiconductor layer has a thickness of less than about 10 nm.
20. The method of Claim 16 further comprising:
forming spaced-apart source and drain regions laterally adjacent the superlattice to define a channel therein;
forming a gate dielectric layer overlying the superlattice; and
a gate electrode layer overlying said gate dielectric layer.
21. The method of Claim 16 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV
semiconductors, Group IH-V semiconductors, and Group II-VI semiconductors; and wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
22. The method of Claim 1 wherein opposing base semiconductor portions in adjacent groups of layers are chemically bound together.