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1. (WO2007005862) SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER AND ASSOCIATED METHODS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005862 International Application No.: PCT/US2006/026029
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
IPC:
H01L 29/15 (2006.01) ,H01L 29/04 (2006.01) ,H01L 29/786 (2006.01) ,H01L 29/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
15
Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
04
characterised by their crystalline structure, e.g. polycrystalline, cubicĀ or particular orientation of crystalline planes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
MEARS TECHNOLOGIES, INC. [US/US]; 1100 Winter Street Suite 4700 Waltham, MA 02451, US (AllExceptUS)
RAO, Kalipatnam Vivek [US/US]; US (UsOnly)
Inventors:
RAO, Kalipatnam Vivek; US
Agent:
REGAN, Christopher F. ; 255 S. Orange Ave. Suite 1401 Orlando, FL 32802-3791, US
Priority Data:
60/695,58830.06.2005US
Title (EN) SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER AND ASSOCIATED METHODS
(FR) DISPOSITIF SEMI-CONDUCTEUR AYANT UNE CONFIGURATION SEMI-CONDUCTEUR SUR ISOLANT (SOI), COMPRENANT UN SUPER-RÉSEAU SUR UNE COUCHE SEMI-CONDUCTRICE ET PROCÉDÉS ASSOCIÉS
Abstract:
(EN) A semiconductor device may include a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The semiconductor device may further include a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
(FR) La présente invention concerne un dispositif semi-conducteur pouvant comprendre un substrat, une couche isolante sur le substrat et une couche semi-conductrice sur la couche isolante sur un côté de celle-ci opposé au substrat. Le dispositif semi-conducteur peut comprendre en outre un super-réseau sur la couche semi-conductrice sur un côté de celle-ci opposé à la couche isolante. Le super-réseau peut comprendre une pluralité de groupes empilés de couches, chaque groupe comprenant une pluralité de monocouches semi-conductrices de base empilées définissant une partie semi-conductrice de base et au moins une monocouche non semi-conductrice sur celle-ci. La monocouche non semi-conductrice peut être contrainte dans un réseau cristallin de parties semi-conductrices de base adjacentes.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1920466JP2008544581CN101278400CA2612243AU2006265096