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1. (WO2007005823) SEMICONDUCTOR WAFER CUTTING BLADE AND METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005823 International Application No.: PCT/US2006/025965
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
IPC:
H01L 21/44 (2006.01) ,H01L 21/46 (2006.01) ,H01L 21/48 (2006.01) ,H01L 21/50 (2006.01) ,H01L 21/78 (2006.01) ,H01L 21/301 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
44
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
46
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428142
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474 Mail Station 3999 Dallas, TX 75265-5474, US (AllExceptUS)
HARRIS, John, Paul, Jr. [US/US]; US (UsOnly)
Inventors:
HARRIS, John, Paul, Jr.; US
Agent:
FRANZ, Warren, L. ; TEXAS INSTRUMENTS INCOPORATED Deputy General Patent Counsel P.O. Box 655474, M/S 3999 Dallas, TX 75265-5474, US
Priority Data:
11/172,97501.07.2005US
Title (EN) SEMICONDUCTOR WAFER CUTTING BLADE AND METHOD
(FR) LAME ET PROCEDE DE COUPE DE TRANCHE A SEMI-CONDUCTEURS
Abstract:
(EN) The invention provides apparatus and methods for sawing and singulating individual devices from a silicon or glass-bonded semiconductor wafer. Using methods of the invention, wafer device singulation includes a step of sawing kerfs approximately coinciding with the peripheries of numerous devices arranged on a wafer. Kerfs are also sawn into the opposite side of the wafer approximately opposing the first kerfs. Mechanical stress is applied to the wafer causing controlled breakage of the intervening wafer material, severing each of the devices from its neighbors. A saw blade (30) apparatus of the invention provides enhanced cutting characteristics and is particularly suited for glass-bonded semiconductor wafer device singulation. The saw blade has a diamond disc (32) suitable for high-speed rotation about its axis. The saw blade of the invention also preferably has a radiused cutting edge (36), and an annular gutter symmetrically disposed about the circumference on each of the opposing planes of the disc.
(FR) L'invention concerne un appareil et des proc�d�s de sciage et ds�paration de dispositifs individuels d'une tranche � semi-conducteurs faite de silicium ou de verre. La s�paration des dispositifs de la tranche selon les proc�d�s de l'invention consiste � former des entailles co�ncidant approximativement avec les contours des nombreux dispositifs form�s sur la tranche. D'autres entailles sont �galement form�es sur le c�t� oppos� de la tranche face aux premi�res entailles. Une contrainte m�canique est appliqu�e sla tranche, provoquant la cassure contr�l�e du mat�riau actif la tranche, s�parant chaque dispositif de ses voisins. L'appareil � lame (30) de scie de l'invention pr�sente des caract�ristiques de coupe am�lior�es, et est particuli�rement adapt� pour la s�paration de dispositifs d'une tranche � semi-conducteurs form�e dverre. La lame de scie pr�sente un disque (32) en diamant adapt pour une rotation � vitesse �lev�e autour de son axe. La lame scie de l'invention pr�sente �galement, de pr�f�rence, un bord tranchant arrondi (36), et un logement de bavure annulaire dispos�de fa�on sym�trique autour de la circonf�rence sur chacun des plans oppos�s du disque.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080028469JP2008544580CN101213645