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1. (WO2007005515) AUTOMATED SERIAL PROTOCOL TARGET PORT TRANSPORT LAYER RETRY MECHANISM
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005515 International Application No.: PCT/US2006/025353
Publication Date: 11.01.2007 International Filing Date: 28.06.2006
IPC:
G06F 13/38 (2006.01) ,H04L 12/56 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12
Data switching networks
54
Store-and-forward switching systems
56
Packet switching systems
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95052, US (AllExceptUS)
LAU, Victor [CN/US]; US (UsOnly)
SETO, Pak-lung [US/US]; US (UsOnly)
CHEMUDUPATI, Suresh [IN/US]; US (UsOnly)
CHANG, Naichih [--/US]; US (UsOnly)
VEMULA, Kiran [IN/US]; US (UsOnly)
HALLECK, William [US/US]; US (UsOnly)
PARIKH, Ankit [IN/US]; US (UsOnly)
Inventors:
LAU, Victor; US
SETO, Pak-lung; US
CHEMUDUPATI, Suresh; US
CHANG, Naichih; US
VEMULA, Kiran; US
HALLECK, William; US
PARIKH, Ankit; US
Agent:
MALLIE, Michael, J. ; BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP 12400 Wilshire Boulevard, 7th Floor Los Angeles, CA 90025, US
Priority Data:
11/171,98530.06.2005US
Title (EN) AUTOMATED SERIAL PROTOCOL TARGET PORT TRANSPORT LAYER RETRY MECHANISM
(FR) MECANISME DE REESSAI DE COUCHE TRANSPORT PAR UN PORT CIBLE DANS UN PROTOCOLE SERIALISE AUTOMATISE
Abstract:
(EN) Disclosed is a target port that implements a transport layer retry (TLR) mechanism. The target port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.
(FR) L'invention se rapporte à un port cible qui met en oeuvre un mécanisme de réessai de couche transport (TLR). Le port cible comprend un circuit ayant une couche transport de transmission et une couche transport de réception, les deux couches transport de transmission et de réception étant couplées à une liaison. Un processeur de protocole de transmission de la couche transport de transmission commande un mécanisme TLR dans un protocole sérialisé. Un processeur de protocole de réception de la couche transport de réception est couplée à la couche transport de transmission et commande également le mécanisme TLR dans le protocole sérialisé.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1899830US20070002827CN101208677