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1. (WO2007005472) A NEW ESD DEVICE WITH LOW TRIGGER VOLTAGE AND LOW LEAKAGE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005472 International Application No.: PCT/US2006/025197
Publication Date: 11.01.2007 International Filing Date: 26.06.2006
IPC:
H02H 9/00 (2006.01) ,H02H 3/22 (2006.01) ,H02H 1/00 (2006.01)
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
H
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
9
Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
H
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
3
Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection
20
responsive to excess voltage
22
of short duration, e.g. lightning
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
H
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
1
Details of emergency protective circuit arrangements
Applicants:
ALTERA CORPORATION [US/US]; 101 Innovation Drive San Jose, CA 95134, US (AllExceptUS)
O, Hugh-sungki [US/US]; US (UsOnly)
SHIH, Chih-Ching [US/US]; US (UsOnly)
HUANG, Cheng-Hsiung [US/US]; US (UsOnly)
LIU, Yow-Juang, Bill [US/US]; US (UsOnly)
Inventors:
O, Hugh-sungki; US
SHIH, Chih-Ching; US
HUANG, Cheng-Hsiung; US
LIU, Yow-Juang, Bill; US
Agent:
MORRIS, Francis, E. ; 1111 Pennsylvania Ave., NW Washington, DC 20004, US
Priority Data:
11/173,25401.07.2005US
Title (EN) A NEW ESD DEVICE WITH LOW TRIGGER VOLTAGE AND LOW LEAKAGE
(FR) NOUVEAU DISPOSITIF ANTISTATIQUE A FAIBLE TENSION DE DECLENCHEMENT ET FAIBLES FUITES
Abstract:
(EN) An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.
(FR) L'invention porte sur un dispositif antistatique comportant: un premier et un deuxième transistor formés sur un substrat et présentant chacun une source, un drain et une grille, la source et le drain du premier transistor étant montés entre la terre et une broche d'E/S ou une entrée, la grille du premier transistor étant reliée à la terre et la source, et le drain du deuxième transistor étant montée entre le substrat du premier transistor et la broche d'E/S ou l'entrée; une première et une deuxième capacité montées en série entre la terre et broche d'E/S ou l'entrée; et au moins un troisième transistor monté entre la terre et un noeud situé entre la première capacité et la deuxième, auquel est également connecté la grille du deuxième transistor.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)