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1. (WO2007005330) SYSTEMS AND METHODS FOR WEIGHTED OVERLAP AND ADD PROCESSING
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005330 International Application No.: PCT/US2006/024450
Publication Date: 11.01.2007 International Filing Date: 23.06.2006
IPC:
G06F 15/00 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
Applicants:
L-3 INTEGRATED SYSTEMS COMPANY [US/US]; 10001 Jack Finney Blvd. Greenville, TX 75402, US (AllExceptUS)
YANCEY, Jerry, W. [US/US]; US (UsOnly)
KUO, Yea, Z. [US/US]; US (UsOnly)
Inventors:
YANCEY, Jerry, W.; US
KUO, Yea, Z.; US
Agent:
ENDERS, William, W.; O'Keefe, Egan & Peterman, LLP 1101 Capital of Texas Highway South Suite C-200 Austin, TX 78746, US
Priority Data:
11/170,79429.06.2005US
Title (EN) SYSTEMS AND METHODS FOR WEIGHTED OVERLAP AND ADD PROCESSING
(FR) SYSTEMES ET PROCEDES DE TRAITEMENT D'UNE ARCHITECTURE DE CHEVAUCHEMENT ET AJOUT PONDEREE
Abstract:
(EN) Systems and methods for providing a weighted overlap and add (WOLA) architecture and/or for providing polyphase WOLA FFT processing that may be employed, for example, for separation or channelization of closely-spaced frequencies of an input signal. A WOLA architecture that may be implemented as first-in-first-out (FIFO) cores in an FPGA or ASIC device. The FIFO cores may be pre-existing (e.g., provided as free FIFO cores in a commercial off the shelf (COTS) FPGA device) or may be custom-programmed into a custom ASIC device.
(FR) L'invention concerne des systèmes et des procédés d'obtention d'une architecture de chevauchement et ajout pondérée (WOLA) et/ou de traitement FFT polyphase de l'architecture WOLA, pouvant être utilisés, par exemple, dans la séparation ou le découpage en canaux de fréquences espacées proches d'un signal d'entrée. L'invention concerne également une architecture WOLA pouvant être mise en oeuvre comme noeuds FIFO dans un dispositif FPGA ou ASIC. Les noeuds FIFO peuvent être pré-existants (par exemple fournis comme noeuds FIFO intégrés dans un dispositif FPGA commercial standard (COTS)), ou peuvent être programmés de manière personnalisée dans un dispositif ASIC personnalisé.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)