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1. (WO2007005046) SYSTEM AND METHOD FOR COMMUNICATING WITH MEMORY DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005046 International Application No.: PCT/US2005/038434
Publication Date: 11.01.2007 International Filing Date: 24.10.2005
IPC:
G06F 13/28 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
20
for access to input/output bus
28
using burst mode transfer, e.g. direct memory access, cycle steal
Applicants:
SIGMATEL, INC. [US/US]; 1601 S. Mo Pac Expressway Suite 100 Austin, TX 78746, US (AllExceptUS)
Inventors:
HENSON, Mathew; US
BAKER, David, Cureton; US
Agent:
TOLER, Jeffrey, G.; 8500 Bluffstone Cove Suite A201 Austin, TX 78759, US
Priority Data:
11/171,91930.06.2005US
Title (EN) SYSTEM AND METHOD FOR COMMUNICATING WITH MEMORY DEVICES
(FR) SYSTEME ET PROCEDE DE MISE EN COMMUNICATION AVEC DES DISPOSITIFS MEMOIRE
Abstract:
(EN) The disclosure is directed to a device (102) including a memory interface (114). The memory interface includes a data interface, a first state machine (1 16) and a second state machine (118). The first state machine includes a first chip select interface and a first ready /busy interface (124, 126). The first state machine is configured to select and monitor a first memory' device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface. The second state machine includes a second chip select interface and a second ready/busy interface. The second state machine is configured to select and monitor a second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.
(FR) Ce dispositif comprend une interface mémoire dotée d'une interface de données, d'une première machine d'état et d'une seconde machine d'état; la première comprend une première interface de sélection de puce et une première interface prête/occupée et est configurée de manière à sélectionner et surveiller un premier dispositif mémoire via la première interface de sélection de puce et la première interface prête/occupée, lorsque le premier dispositif mémoire est couplé à l'interface de données; la seconde machine d'état comprend une seconde interface de sélection de puce et une seconde interface prête/occupée et est configurée de manière à sélectionner et surveiller un second dispositif mémoire via la seconde interface de sélection de puce et la seconde interface prête/occupée, lorsque le second dispositif de mémoire est couplé à l'interface de données.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN101133404