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1. (WO2007005042) ESD COMPONENT GROUND CLIP
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/005042 International Application No.: PCT/US2005/035839
Publication Date: 11.01.2007 International Filing Date: 04.10.2005
IPC:
G01R 1/04 (2006.01) ,G01R 31/28 (2006.01) ,H01R 13/648 (2006.01) ,H05F 3/02 (2006.01) ,H01L 23/60 (2006.01) ,H05K 9/00 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
1
Details of instruments or arrangements of the types covered by groups G01R5/-G01R13/122
02
General constructional details
04
Housings; Supporting members; Arrangements of terminals
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
R
ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
13
Details of coupling devices of the kinds covered by groups H01R12/7087
648
Protective earth or shield arrangements on coupling devices
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
F
STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
3
Carrying-off electrostatic charges
02
by means of earthing connections
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
60
Protection against electrostatic charges or discharges, e.g. Faraday shields
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
9
Screening of apparatus or components against electric or magnetic fields
Applicants:
HONEYWELL INTERNATIONAL INC. [US/US]; 101 Columbia Road P.O. Box 2245 Morristown, NJ 07960, US (AllExceptUS)
SUNDSTROM, Lance [US/US]; US (UsOnly)
Inventors:
SUNDSTROM, Lance; US
Agent:
HOIRIIS, David ; Honeywell International Inc. 101 Columbia Road P.O. Box 2245 Morristown, NJ 07960, US
Priority Data:
11/030,65704.01.2005US
Title (EN) ESD COMPONENT GROUND CLIP
(FR) COLLIER DE MISE A LA TERRE A COMPOSANT ESD
Abstract:
(EN) An ESD protection system for an IC device. An ESD protection circuit is comprised of a plurality of resistors and a common ground bus. The first terminal of each resistor is coupled to an associated pin of an IC device while the second terminal of each resistor is coupled to the common ground bus. The common ground bus is coupled with a reference ground. A clip holds the ESD protection circuit to pins of the IC device. As the IC device is transported, the resent invention maintains a continuous controlled DC path to reference ground on every pin of the IC device, thus preventing damaging electrostatic charges from accumulating on the IC device pins, or discharging though the IC device.
(FR) Un système de protection ESD pour circuit intégré présente un circuit de protection doté d'une pluralité de résistances et d'un bus de mise à la terre commun. La première borne de chaque résistance est couplée à une broche associée d'un circuit intégré, alors que la seconde borne de chaque résistance est couplée au bus de mise à la terre commun qui est couplé, à son tour, avec une masse de référence. Un collier maintient le circuit de protection ESD sur les broches du circuit intégré. Lors du transport de ce dernier, le système de protection ESD conserve un trajet en continu CC contrôlé comme masse de référence sur chaque broche du circuit intégré, avec pour effet d'éviter l'endommagement des charges électrostatiques, l'accumulation sur les broches du circuit intégré ou leur décharge sur le circuit intégré.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)