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1. (WO2007004550) METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR WAFER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/004550 International Application No.: PCT/JP2006/313082
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
IPC:
H01L 21/205 (2006.01) ,C23C 16/02 (2006.01) ,H01L 21/26 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
02
Pretreatment of the material to be coated
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
Applicants:
コマツ電子金属株式会社 KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA [JP/JP]; 〒2540014 神奈川県平塚市四之宮3丁目25番1号 Kanagawa 25-1, Shinomiya 3-chome, Hiratsuka-shi, Kanagawa 2540014, JP (AllExceptUS)
那須 悠一 NASU, Yuichi [JP/JP]; JP (UsOnly)
加藤 裕孝 KATOU, Hirotaka [JP/JP]; JP (UsOnly)
楢原 和宏 NARAHARA, Kazuhiro [JP/JP]; JP (UsOnly)
松永 秀幸 MATSUNAGA, Hideyuki [JP/JP]; JP (UsOnly)
Inventors:
那須 悠一 NASU, Yuichi; JP
加藤 裕孝 KATOU, Hirotaka; JP
楢原 和宏 NARAHARA, Kazuhiro; JP
松永 秀幸 MATSUNAGA, Hideyuki; JP
Agent:
木村 高久 KIMURA, Takahisa; 〒1040043 東京都中央区湊1丁目8番11号 千代ビル6階 Tokyo 6F, Sendai Building, 8-11, Minato 1-chome, Chuo-ku, Tokyo 1040043, JP
Priority Data:
2005-19788706.07.2005JP
Title (EN) METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR WAFER
(FR) PROCÉDÉ ET APPAREIL DE FABRICATION D’UNE GALETTE EN SEMI-CONDUCTEUR
(JA) 半導体ウェーハの製造方法および製造装置
Abstract:
(EN) A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using such semiconductor wafer, by preventing warping from being generated at a stage of a placing process, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front plane temperature and a wafer rear plane temperature is maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with a lift pin or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600°C), and the lift pin is brought into contact with the wafer rear plane.
(FR) La présente invention concerne un procédé et un appareil de fabrication d’une galette en semi-conducteur permettant d’améliorer la qualité de la galette en semi-conducteur, et en outre d’améliorer la qualité d’un dispositif semi-conducteur fabriqué à partir d’une telle galette en semi-conducteur, par la prévention de l'apparition de distorsion pendant le processus de placement, au moment d’effectuer le traitement thermique sur un substrat de galette en semi-conducteur. Le processus de placement est effectué par un moyen de placement de façon que le moment où la différence de température entre le plan avant de la galette et le plan arrière de la galette est maximale, et le moment où la distorsion apparaît dans la galette sont antérieurs au moment où la galette est mise en contact avec une broche de levage ou un suscepteur (c.-à-d. le moment après que la température a atteint sa limite supérieure d’une zone de température infrarouge à 600°C), et où la broche de levage est mise en contact avec le plan arrière de la galette.
(JA)  半導体ウェーハ基板を熱処理するに際して、移載工程の段階では反りを生じさせないようにして、半導体ウェーハの品質、ひいてはそれによって製造される半導体デバイスの品質を高品質にするための半導体ウェーハの製造方法およびその製造装置に関する発明である。本発明では、ウェーハ表面温度とウェーハ裏面温度との温度差が最大値になるタイミング、ウェーハで反りが発生するタイミングが、リフトピン若しくはサセプタに接触する前となるように(赤外線温度領域の上限値である600゜Cとなる時刻よりも後の時期に)、移載手段による移載処理を実行して、リフトピンをウェーハ裏面に接触させる。
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2007004550US20090226293JP5092162