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1. (WO2007004528) METHOD FOR DESIGNING STRUCTURE OF SILICON CARBIDE ELECTROSTATIC INDUCTION TRANSISTOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/004528    International Application No.:    PCT/JP2006/313046
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
Chapter 2 Demand Filed:    27.04.2007    
IPC:
H01L 29/80 (2006.01), H01L 21/337 (2006.01), H01L 29/808 (2006.01)
Applicants: YAMANASHI UNIVERSITY [JP/JP]; 4-37, Takeda 4-chome, Kofu-shi, Yamanashi 4008510 (JP) (AE, AG, AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GW, HN, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, MG, MK, ML, MN, MR, MW, MX, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SI, SK, SL, SM, SN, SY, SZ, TD, TG, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW only).
National Institute of Advanced Industrial Science and Technology [JP/JP]; 1-3-1, Kasumigaseki, Chiyoda-ku, Tokyo 1008921 (JP) (AE, AG, AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GW, HN, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, MG, MK, ML, MN, MR, MW, MX, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SI, SK, SL, SM, SN, SY, SZ, TD, TG, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW only).
YANO, Koji [JP/JP]; (JP) (For US Only).
KASUGA, Masanobu [JP/JP]; (JP) (For US Only).
YATSUO, Tsutomu [JP/JP]; (JP) (For US Only).
TANAKA, Yasunori [JP/JP]; (JP) (For US Only).
OKAMOTO, Mitsuo [JP/JP]; (JP) (For US Only)
Inventors: YANO, Koji; (JP).
KASUGA, Masanobu; (JP).
YATSUO, Tsutomu; (JP).
TANAKA, Yasunori; (JP).
OKAMOTO, Mitsuo; (JP)
Agent: ISHIKAWA, Hidetake; 26-1-114, Higashi-yurigaoka 3-chome Asao-ku, Kawasaki-shi Kanagawa 2150012 (JP)
Priority Data:
2005-191763 30.06.2005 JP
Title (EN) METHOD FOR DESIGNING STRUCTURE OF SILICON CARBIDE ELECTROSTATIC INDUCTION TRANSISTOR
(FR) PROCÉDÉ POUR CONCEVOIR UNE STRUCTURE DE TRANSISTOR À INDUCTION ÉLECTROSTATIQUE EN CARBURE DE SILICIUM
(JA) 炭化珪素静電誘導トランジスタ構造の設計方法
Abstract: front page image
(EN)When the parameters of the channel structure of a normally-on silicon carbide electrostatic induction transistor, i.e. channel length xj, half channel width a, and channel donor impurity concentration Nch, are determined, a combination of a and Nch satisfying an expression 2.1×107/√Nch<a<1.72×108/√Nch concerning the limits of characteristic on resistance and breakdown voltage is determined, and xj of 4 μm or less satisfying an expression a<-0.1+0.9 xj-0.1 xj2 is also determined (a and xj have a unit of μm, Nch has a unit of cm-3).
(FR)Dans la présente invention, lorsque les paramètres de la structure de canal d'un transistor à induction électrostatique en carbure de silicium normalement activé, par exemple une longueur de canal xj, une largeur de demi-canal a et la concentration en impuretés du donneur du canal Nch, sont déterminés, une combinaison de a et de Nch satisfaisant à une expression 2,1x107/√Nch < a < 1,72x108/√Nch concernant les limites des caractéristiques de résistance et de tension de claquage est déterminée et xj de 4 µm ou moins, satisfaisant à une expression a < -0,1+0,9 xj-0,1 xj2 est aussi déterminé (l’unité de a et xj est le µm et celle de Nch le cm-3).
(JA)not available
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)