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1. (WO2007004295) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/004295 International Application No.: PCT/JP2005/012404
Publication Date: 11.01.2007 International Filing Date: 05.07.2005
IPC:
H01L 21/8246 (2006.01) ,H01L 27/105 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
Applicants:
富士通株式会社 FUJITSU LIMITED [JP/JP]; 〒2118588 神奈川県川崎市中原区上小田中4丁目1番1号 Kanagawa 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi, Kanagawa 2118588, JP (AllExceptUS)
高橋 誠 TAKAHASHI, Makoto [JP/JP]; JP (UsOnly)
永井 孝一 NAGAI, Kouichi [JP/JP]; JP (UsOnly)
Inventors:
高橋 誠 TAKAHASHI, Makoto; JP
永井 孝一 NAGAI, Kouichi; JP
Agent:
國分 孝悦 KOKUBUN, Takayoshi; 〒1700013 東京都豊島区東池袋1丁目17番8号 池袋TGホーメストビル5階 Tokyo 5th Floor, Ikebukuro TG Homest Building 17-8, Higashi-Ikebukuro 1-chome Toshima-ku, Tokyo 1700013, JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) A surface of a lower layer insulating film (55) is planarized by CMP method or the like, and an upper layer insulating film (56) and a metal protecting film (59) are formed on the lower layer insulating film (55). Therefore, the upper layer insulating film (56) and the metal protecting film (59) are formed in a status having excellent coverage, and a water/hydrogen blocking function of the upper layer insulating film (56) and the metal protecting film (59) are maximized.
(FR) La présente invention concerne un procédé consistant à planariser une surface d’un film isolant de couche inférieure (55) par polissage chimico-mécanique ou procédé similaire, et à former un film isolant de couche supérieure (56) et un film de protection métallique (59) sur le film isolant de couche inférieure (55). Ainsi, le film isolant de couche supérieure (56) et le film de protection métallique (59) obtenus présentent une excellente couverture, et une fonction d’étanchéité/blocage d’hydrogène du premier film (56) et du second film (59) est optimisée.
(JA)  本発明では、下層絶縁膜(55)の表面をCMP法等により平坦化し、この下層絶縁膜(55)上に上層絶縁膜(56)や金属保護膜(59)を形成する。従って、上層絶縁膜(56)及び金属保護膜(59)がカバレッジに優れた状態に形成されることになり、上層絶縁膜(56)及び金属保護膜(59)の水・水素の遮蔽機能を最大限に発揮させることができる。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20080142864CN101213655JP4998262