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Machine translation
1. (WO2007004289) TESTING CIRCUIT, WAFER, MEASURING APPARATUS, DEVICE MANUFACTURING METHOD AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/004289    International Application No.:    PCT/JP2005/012359
Publication Date: 11.01.2007 International Filing Date: 04.07.2005
IPC:
H01L 29/78 (2006.01), G01R 31/26 (2006.01), G01R 31/28 (2006.01), H01L 21/66 (2006.01), H01L 21/822 (2006.01), H01L 27/04 (2006.01)
Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY [JP/JP]; 1-1, Katahira 2-chome, Aoba-ku, Sendai, Miyagi 9808577 (JP) (For All Designated States Except US).
SUGAWA, Shigetoshi [JP/JP]; (JP) (For US Only).
TERAMOTO, Akinobu [JP/JP]; (JP) (For US Only)
Inventors: SUGAWA, Shigetoshi; (JP).
TERAMOTO, Akinobu; (JP)
Agent: RYUKA, Akihiro; 5F, Shinjuku Square Tower 22-1, Nishi-Shinjuku 6-chome Shinjuku-ku, Tokyo 163-1105 (JP)
Priority Data:
Title (EN) TESTING CIRCUIT, WAFER, MEASURING APPARATUS, DEVICE MANUFACTURING METHOD AND DISPLAY DEVICE
(FR) CIRCUIT DE TEST, GALETTE, APPAREIL DE MESURE, PROCÉDÉ DE FABRICATION DU DISPOSITIF ET DISPOSITIF D’AFFICHAGE
(JA) テスト用回路、ウェハ、測定装置、デバイス製造方法、及び表示装置
Abstract: front page image
(EN)A testing circuit is provided with a plurality of transistors, which are to be measured and electrically arranged in parallel; a selecting section for sequentially selecting the transistors to be measured; and an output section for sequentially outputting source voltages of the transistors sequentially selected by the selecting section.
(FR)La présente invention concerne un circuit de test comportant une pluralité de transistors, dont les caractéristiques doivent être mesurées et qui sont électriquement connectés en parallèle ; une section de sélection pour sélectionner séquentiellement les transistors à vérifier ; et une section de sortie pour émettre séquentiellement les tensions de source des transistors sélectionnés séquentiellement par la section de sélection.
(JA) 電気的に並列に設けられた複数の被測定トランジスタと、それぞれの被測定トランジスタを順次選択する選択部と、選択部が順次選択した被測定トランジスタのソース電圧を順次出力する出力部とを有するテスト用回路を提供する。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)