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1. (WO2007004182) DIFFERENTIAL MULTIPHASE FREQUENCY DIVIDER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/004182 International Application No.: PCT/IB2006/052216
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
IPC:
H03K 5/15 (2006.01) ,H03K 23/54 (2006.01) ,H03K 3/356 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
5
Manipulating pulses not covered by one of the other main groups in this subclass
15
Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
50
using bi-stable regenerative trigger circuits
54
Ring counters, i.e. feedback shift register counters
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
Applicants:
NXP B.V. [NL/NL]; High Tech Campus 60 NL-5656 AG Eindhoven, NL (AllExceptUS)
U.S. PHILIPS CORPORATION [US/US]; 1251 Avenue Of The Americas New York, New York 10020, US (AE)
SONG, Wenyi [CA/US]; NL (UsOnly)
Inventors:
SONG, Wenyi; NL
Agent:
ZAWILSKI, Peter; NXP Semiconductors Intellectual Property Department 1109 McKay Drive, M/S-41SJ San Jose, CA 95131-1706, US
Priority Data:
60/696,49030.06.2005US
Title (EN) DIFFERENTIAL MULTIPHASE FREQUENCY DIVIDER
(FR) DIVISEUR DE FREQUENCE MULTIPHASE DIFFERENTIEL
Abstract:
(EN) A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one latch stage are connected to the corresponding differential D-inputs of the next latch stage. For even numbers of latch stages, the differential clock inputs of each are connected together and alternately to the divider clock input and its complement. The last differential Q-output is returned and cross- connected to the differential D-inputs of the first latch stage. For odd numbers of latch stages, the differential clock inputs of each are respectively connected in parallel to the divider clock input and its complement. The last differential Q-output is returned and straight-connected to the differential D-inputs of the first latch stage.
(FR) Un diviseur multiphase comprend plusieurs verrous différentiels connectés dans un anneau. Le nombre de verrous dans l'anneau est égal au nombre de phases produites et au diviseur appliqué à l'horloge d'entrée. Les sorties Q d'un étage de verrou sont connectées aux entrées D différentielles correspondantes de l'étage de verrou suivant. Pour les nombres pairs d'étages de verrou, les entrées d'horloge différentielles sont connectées les unes aux autres ou à l'entrée de l'horloge du diviseur et son complément. La dernière sortie Q différentielle est renvoyée et interconnectée aux entrées D différentielles du premier étage de verrou. Pour les nombres impairs des étages de verrou, les entrées d'horloge différentielles de chacun sont respectivement connectées en parallèle à l'entrée de l'horloge du diviseur et son complément. La dernière entrée Q différentielle est renvoyée et connectée de manière directe aux entrées D différentielles du premier étage de verrou.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1900097JP2008545321US20090153201CN101213747