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1. (WO2007004181) MULTI-BIT PROGRAMMABLE FREQUENCY DIVIDER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/004181 International Application No.: PCT/IB2006/052215
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
IPC:
H03K 23/66 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
66
with a variable counting base, e.g. by presetting or by adding or suppressing pulses
Applicants:
KONINKLIJKE PHILIPS ELECTRONICS, N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL (AllExceptUS)
U.S. PHILIPS CORPORATION [US/US]; 1251 Avenue Of The Americas New York, New York 10020, US (AE)
SONG, Wenyi [CA/US]; NL (UsOnly)
JOORDENS, Geertjan [NL/US]; NL (UsOnly)
Inventors:
SONG, Wenyi; NL
JOORDENS, Geertjan; NL
Agent:
ZAWILSKI, Peter; NXP Semiconductors Intellectual Property Department 1109 McKay Drive, M/S-41SJ San Jose, CA 95131-1706, US
Priority Data:
60/696,36530.06.2005US
Title (EN) MULTI-BIT PROGRAMMABLE FREQUENCY DIVIDER
(FR) DIVISEUR DE FREQUENCE PROGRAMMABLE MULTIBIT
Abstract:
(EN) A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization.
(FR) Un diviseur de fréquence numérique, modulaire, programmable et multibit divise une fréquence d'entrée par un diviseur entier à m bits pour produire une fréquence de sortie. Le diviseur entier réinitialise m nombres d'étages de bascules bistables par l'entrée du diviseur à la fin de chaque horloge de sortie. Chaque bit de diviseur est aiguillé vers une entrée D par un multiplexeur de données respectif commandé par une sortie d'horloge. Un pilote à modes d'initialisation/d'exécution reçoit la fréquence d'entrée, produit la fréquence de sortie divisée et commande la synchronisation de la réinitialisation.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1900099JP2008545320US20080258781CN101213749