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1. (WO2007003984) DEVICE AND METHOD FOR ARBITRATING BETWEEN DIRECT MEMORY ACCESS TASK REQUESTS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/003984 International Application No.: PCT/IB2005/052173
Publication Date: 11.01.2007 International Filing Date: 30.06.2005
IPC:
G06F 13/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
20
for access to input/output bus
28
using burst mode transfer, e.g. direct memory access, cycle steal
30
with priority control
Applicants:
FREESCALE SEMICONDUCTOR, INC. [US/US]; 7700 West Parmer Lane Austin, TX 78729, US (AllExceptUS)
SHASHA, Uri [IL/IL]; IL (UsOnly)
GURFINKEL, Sagi [IL/IL]; IL (UsOnly)
HASSID, Gilad [IL/IL]; IL (UsOnly)
KAHN, Eran [IL/IL]; IL (UsOnly)
SHVAGER, Yehuda [IL/IL]; IL (UsOnly)
Inventors:
SHASHA, Uri; IL
GURFINKEL, Sagi; IL
HASSID, Gilad; IL
KAHN, Eran; IL
SHVAGER, Yehuda; IL
Agent:
FREESCALE SEMICONDUCTOR INC.; c/o FERRO, Fredo, Nunes Freescale Semiconducteurs France SAS 134, avenue Eisenhower, BP 72329 31023 Toulouse, FR
Priority Data:
Title (EN) DEVICE AND METHOD FOR ARBITRATING BETWEEN DIRECT MEMORY ACCESS TASK REQUESTS
(FR) DISPOSITIF ET PROCEDE D'ARBITRAGE ENTRE DES REQUETES DE TACHE D'ACCES DIRECT A LA MEMOIRE
Abstract:
(EN) A method (500) for arbitrating between direct memory access (DMA) task requests, the method (500) includes receiving (510) multiple DMA task requests; the method is characterized by selecting (520) a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device (90) that includes an interface (420), that is adapted to receive DMA task requests; the device (400) is characterized by including an arbiter (410) that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.
(FR) L'invention concerne un procédé (500) d'arbitrage entre des requêtes de tâche d'accès direct à la mémoire (DMA). Ce procédé (500) consiste : à recevoir (510) plusieurs requêtes de tâche DMA ; et à sélectionner (520) une requête de tâche DMA parmi les multiples requêtes de tâche DMA en réponse à des échéances temporelles associées aux tâches DMA. L'invention concerne également un dispositif (90) qui comprend une interface (420) conçue pour recevoir des requêtes de tâche DMA. Ledit dispositif (400) est caractérisé en ce qu'il comprend un arbitre (410) conçu pour sélectionner une tâche DMA parmi les multiples requêtes de tâche DMA en réponse aux échéances temporelles associées aux tâches DMA.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1899828JP2009505169US20090216917JP4598858CN101218570