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1. (WO2007003370) A MEMORY ARRANGEMENT FOR MULTI-PROCESSOR SYSTEMS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/003370 International Application No.: PCT/EP2006/006375
Publication Date: 11.01.2007 International Filing Date: 30.06.2006
Chapter 2 Demand Filed: 30.04.2007
IPC:
G06F 15/76 (2006.01) ,G06F 13/16 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
Applicants:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW [BE/BE]; Kapeldreef 75 B-3001 Leuven, BE (AllExceptUS)
SAMSUNG ELECTRONICS CO., LTD. [KR/KR]; 416, Maetan-dong Yeongtong-gu Suwon-si Gyeonggi-do, KR (AllExceptUS)
MEI, Bingfeng [CN/CN]; CN (UsOnly)
KIM, Suk, Jin [KR/KR]; KR (UsOnly)
ALLAM, Osman [GR/BE]; BE (UsOnly)
Inventors:
MEI, Bingfeng; CN
KIM, Suk, Jin; KR
ALLAM, Osman; BE
Agent:
BIRD, William, E. ; Bird Goën & Co Klein Dalenstraat 42A B-3020 Winksele, BE
Priority Data:
60/695,50630.06.2005US
Title (EN) A MEMORY ARRANGEMENT FOR MULTI-PROCESSOR SYSTEMS
(FR) AGENCEMENT MEMOIRE POUR SYSTEMES MULTIPROCESSEURS
Abstract:
(EN) A hardware memory architecture or arrangement is proposed, suited for multi-processor systems or arrays. The invention is to add between a functional unit (computation unit) and at least one memory device, which said functional unit accesses (for write and/or read), at least one memory queue.
(FR) L'invention concerne une architecture ou un agencement de mémoire matériel destiné(e) à des systèmes ou des réseaux multiprocesseurs. Le dispositif de l'invention peut s'ajouter entre une unité fonctionnelle (unité de calcul) et au moins un dispositif mémoire, ladite unité fonctionnelle accédant (pour écrire et/ou lire) à au moins une file d'attente mémoire.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080025053EP1896983EP2317446JP2008545187