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1. (WO2007002695) LAYOUT MODIFICATION TO ELIMINATE LINE BENDING CAUSED BY LINE MATERIAL SHRINKAGE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/002695 International Application No.: PCT/US2006/025031
Publication Date: 04.01.2007 International Filing Date: 26.06.2006
IPC:
H01L 21/461 (2006.01) ,H01L 21/302 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
46
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428142
461
to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US (AllExceptUS)
UKRAINTSEV, Vladimir, Alexeevich [US/US]; US (UsOnly)
MASON, Mark, E. [US/US]; US (UsOnly)
BLATCHFORD, James, Walter [US/US]; US (UsOnly)
SMITH, Brian, Ashley [US/US]; US (UsOnly)
HORNUNG, Brian, Edward [US/US]; US (UsOnly)
ANDERSON, Dirk, Noel [US/US]; US (UsOnly)
Inventors:
UKRAINTSEV, Vladimir, Alexeevich; US
MASON, Mark, E.; US
BLATCHFORD, James, Walter; US
SMITH, Brian, Ashley; US
HORNUNG, Brian, Edward; US
ANDERSON, Dirk, Noel; US
Agent:
FRANZ, Warren, L. ; Deputy General Patent Counsel Texas Instruments Incorporated P.O. Box 655474, M/s 3999 Dallas, TX 75265-5474, US
Priority Data:
11/165,23224.06.2005US
Title (EN) LAYOUT MODIFICATION TO ELIMINATE LINE BENDING CAUSED BY LINE MATERIAL SHRINKAGE
(FR) MODIFICATION DE CONFIGURATION DESTINEE A ELIMINER LE PLIAGE D'UNE LIGNE CAUSE PAR UNE REDUCTION DU MATERIAU DE LA LIGNE
Abstract:
(EN) A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature (271) disposed adjacent to an outside of a corner feature (250).
(FR) L'invention concerne un dispositif à semi-conducteurs et un procédé de fabrication d'un dispositif à semi-conducteurs avec un pliage de ligne réduit. Ledit procédé consiste à former une première couche et à déposer une couche de photorésine sur la première couche. La couche de photorésine peut être modélisée, de manière à présenter au moins un élément (271) de support disposé de manière adjacente à la partie extérieure d'un élément (250) en coin.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
JP2008547231US20060292885CN101203951