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1. (WO2007002551) MEMORY MICRO-TILING
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/002551 International Application No.: PCT/US2006/024728
Publication Date: 04.01.2007 International Filing Date: 23.06.2006
IPC:
G06F 13/16 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95052, US (AllExceptUS)
AKIYAMA, James [US/US]; US (UsOnly)
CLIFFORD, William [US/US]; US (UsOnly)
OSBORNE, Randy [CA/US]; US (UsOnly)
Inventors:
AKIYAMA, James; US
CLIFFORD, William; US
OSBORNE, Randy; US
Agent:
VINCENT, Lester J. ; BLAKELY SOKOLOFF TAYLOR & ZAFMAN 12400 Wilshire Boulevard||7th Floor Los Angeles, California 90025, US
Priority Data:
11/159,74523.06.2005US
Title (EN) MEMORY MICRO-TILING
(FR) MICRO-PAVAGE DE MEMOIRE
Abstract:
(EN) According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
(FR) Un mode de réalisation de l'invention concerne un contrôleur de mémoire. Ce contrôleur de mémoire comprend une logique d'affectation et un assembleur de transaction. La logique d'affectation est conçue pour recevoir une demande d'accès à un canal de mémoire. L'assembleur de transaction est conçu pour associer la demande à une ou plusieurs demandes supplémentaires d'accès à au moins deux sous-canaux adressables indépendamment dans ledit canal.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080014066EP1894110JP2008544414