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Machine translation
1. (WO2007002426) SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/002426    International Application No.:    PCT/US2006/024516
Publication Date: 04.01.2007 International Filing Date: 20.06.2006
IPC:
H01L 21/306 (2006.01), H01L 21/336 (2006.01), H01L 21/84 (2006.01), H01L 29/786 (2006.01), H01L 29/04 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard, Santa Clara, California 95052 (US) (For All Designated States Except US).
BRASK, Justin [US/US]; (US) (For US Only).
KAVALIEROS, Jack [US/US]; (US) (For US Only).
DOYLE, Brian [IE/US]; (US) (For US Only).
SHAH, Uday [NP/US]; (US) (For US Only).
DATTA, Suman [IN/US]; (US) (For US Only).
MAJUMDAR, Amlan [IN/US]; (US) (For US Only).
CHAU, Robert [US/US]; (US) (For US Only)
Inventors: BRASK, Justin; (US).
KAVALIEROS, Jack; (US).
DOYLE, Brian; (US).
SHAH, Uday; (US).
DATTA, Suman; (US).
MAJUMDAR, Amlan; (US).
CHAU, Robert; (US)
Agent: VINCENT, Lester J.; BLAKELY SOKOLOFF TAYLOR & ZAFMAN, 12400 Wilshire Boulevard, 7th Floor, Los Angeles, California 90025 (US)
Priority Data:
11/158,661 21.06.2005 US
Title (EN) SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
(FR) STRUCTURES DE DISPOSITIFS SEMI-CONDUCTRICES ET PROCEDES DESTINES A FORMER DES STRUCTURES SEMI-CONDUCTRICES
Abstract: front page image
(EN)A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
(FR)L'invention concerne un procédé de formation de motif sur un film semi-conducteur. Selon un mode de réalisation de la présente invention, un matériau de masque dur est formé sur un film de silicium présentant une orientation cristalline globale, le film semi-conducteur comprenant un premier plan cristallin et un second plan cristallin, le premier plan cristallin étant plus dense que le second plan cristallin, le masque dur étant formé sur le second plan cristallin. Ensuite, le masque dur et le film semi-conducteur sont soumis à une formation de motif en vue de l'obtention d'une structure semi-conductrice recouverte d'un masque dur. La structure semi-conductrice recouverte d'un masque dur est alors soumise à une opération de gravure humide présentant une action chimique suffisante pour graver le second plan cristallin mais insuffisante pour graver le premier plan cristallin.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)