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1. (WO2007002324) AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/002324 International Application No.: PCT/US2006/024360
Publication Date: 04.01.2007 International Filing Date: 23.06.2006
IPC:
G11C 5/06 (2006.01) ,G06F 13/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
06
Arrangements for interconnecting storage elements electrically, e.g. by wiring
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Applicants:
METARAM, INC. [US/US]; 181 Metro Drive San Jose, CA 95110, US (AllExceptUS)
RAJAN, Suresh, N. [US/US]; US
Inventors:
RAJAN, Suresh, N.; US
Agent:
STATTLER, John; Stattler - Suh, PC 60 South Market Street Suite 480 San Jose, CA 95113, US
Priority Data:
60/693,63124.06.2005US
Title (EN) AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT
(FR) NOYAU DE MEMOIRE INTEGRE ET CIRCUIT D'INTERFACE MEMOIRE
Abstract:
(EN) A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.
(FR) Un dispositif mémoire comprend une première et une deuxième puce de circuit intégrée. La première puce de circuit intégré comprend un noyau mémoire ainsi qu'un premier circuit d'interface. Le premier circuit d'interface permet un accès sans restriction aux cellules mémoires (p. ex. opérations de lecture, écriture, activation, préchargement et rafraîchissement des cellules mémoire). La deuxième puce de circuit intégré comprend une deuxième interface qui met en interface le noyau de mémoire, via le premier circuit d'interface, un bus externe, telle qu'une interface synchrone et un bus externe. Une technique combine les puces de circuit intégré de noyau de mémoire et les puces de circuit intégré d'interface pour configurer un dispositif mémoire. On réalise un test de vitesse sur les puces de circuit intégré de noyau de mémoire et les puces de circuit intégré d'interface sont couplées électriquement à la puce de circuit intégré de noyau de mémoire en fonction de la vitesse de la puce de circuit intégré de noyau de mémoire.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080039877JP2008544437KR1020130033456KR1020140037283