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1. (WO2007002215) METHODS FOR FORMING A TRANSISTOR AND MODULATING CHANNEL STRESS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/002215 International Application No.: PCT/US2006/024174
Publication Date: 04.01.2007 International Filing Date: 20.06.2006
IPC:
H01L 21/8238 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
APPLIED MATERIALS, INC. [US/US]; 3050 Bowers Avenue Santa Clara, CA 95054, US (AllExceptUS)
THIRUPAPULIYUR, Sunderraj [IN/US]; US (UsOnly)
NOURI, Faran [US/US]; US (UsOnly)
WASHINGTON, Lori [US/US]; US (UsOnly)
Inventors:
THIRUPAPULIYUR, Sunderraj; US
NOURI, Faran; US
WASHINGTON, Lori; US
Agent:
SERVILLA, Scott, S.; DIEHL SERVILLA LLC 77 Brant Avenue, Suite 110 Clark, NJ 07066, US
Priority Data:
11/165,28223.06.2005US
Title (EN) METHODS FOR FORMING A TRANSISTOR AND MODULATING CHANNEL STRESS
(FR) PROCEDE SERVANT A FABRIQUER UN TRANSISTOR ET A MODULER LES CONTRAINTES EXERCEES SUR LES CANAUX
Abstract:
(EN) Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.
(FR) L'invention concerne des procédés servant à fabriquer des transistors et à modifier les contraintes s'exerçant dans la zone du canal d'un transistor unique. Ceci consiste à modifier un ou plusieurs paramètres exerçant un effet sur les contraintes de la zone du canal, pour un seul transistor, de manière à augmenter ou à diminuer ces contraintes dans des transistors PMOS et NMOS.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)