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1. (WO2007001988) STRUCTURE AND METHOD FOR FORMING LATERALLY EXTENDING DIELECTRIC LAYER IN A TRENCH-GATE FET
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/001988 International Application No.: PCT/US2006/023819
Publication Date: 04.01.2007 International Filing Date: 19.06.2006
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01) ,H01L 23/58 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
Applicants:
FAIRCHILD SEMICONDUCTOR CORPORATION [US/US]; 82 Running Hill Road South Portland, Maine 04106, US (AllExceptUS)
ANDREWS, John, Tracey [US/US]; US (UsOnly)
Inventors:
ANDREWS, John, Tracey; US
Agent:
SANI, Barmak ; TOWNSEND AND TOWNSEND AND CREW LLP Two Embarcadero Center 8th Floor San Francisco, California 94111-3834, US
Priority Data:
11/166,35624.06.2005US
Title (EN) STRUCTURE AND METHOD FOR FORMING LATERALLY EXTENDING DIELECTRIC LAYER IN A TRENCH-GATE FET
(FR) STRUCTURE ET PROCEDE POUR FORMER UNE COUCHE DIELECTRIQUE SE DEPLOYANT LATERALEMENT DANS UN TRANSISTOR TEC A TRANCHEE-GRILLE
Abstract:
(EN) A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer inside and outside the trench. The protective layer is partially removed such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the protective layer.
(FR) L'invention concerne un transistor à effet de champ (TEC) formé selon le procédé comportant les étapes suivantes: former une tranchée dans une région de silicium; former une couche barrière d'oxydation sur une surface de la région de silicium adjacente à la tranchée, et suivant les parois latérales et le fond de la tranchée; former une couche de protection sur la couche barrière d'oxydation, à l'intérieur et à l'extérieur de la tranchée; éliminer partiellement la couche de protection de manière à exposer une partie de la couche barrière d'oxydation se déployant au moins sur le fond de la tranchée, et à faire en sorte que les parties de la couche barrière d'oxydation se déployant sur la surface de la région de silicium adjacente à la tranchée restent couvertes par les parties restantes de la couche de protection.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080025158JP2008547225CN101558499