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1. (WO2007001855) A METHOD OF MAKING A METAL GATE SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Considered void 06.07.2007


Pub. No.: WO/2007/001855 International Application No.: PCT/US2006/023121
Publication Date: 04.01.2007 International Filing Date: 13.06.2006
IPC:
H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
FREESCALE SEMICONDUCTOR, INC. [US/US]; 6501 William Cannon Drive West Law Department Austin, Texas 78735, US (AllExceptUS)
ANDRE, Thomas W. [US/US]; US (UsOnly)
SUBRAMANIAN, Chitra K. [US/US]; US (UsOnly)
Inventors:
ANDRE, Thomas W.; US
SUBRAMANIAN, Chitra K.; US
Agent:
KING, Robert L. ; 7700 West Parmer Lane MD: Tx32/pl02 Austin, Texas 78729, US
Priority Data:
11/166,13924.06.2005US
Title (EN) A METHOD OF MAKING A METAL GATE SEMICONDUCTOR DEVICE
(FR) PROCEDE DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR A GRILLE METALLIQUE
Abstract:
(EN) A patterned polysilicon gate (18) is over a metal layer (16) that is over a gate dielectric layer (14), which in turn is over a semiconductor substrate (12). A thin layer (20) of material is conformally deposited over the polysilicon gate (18) and the exposed metal layer (16) and then etched back to form a sidewall spacer (22) on the polysilicon gate (18) and to re-expose the previously exposed portion of the metal layer (16). The re-exposed metal layer (16) is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer (22). Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate (18) but for the protection provided by the sidewall spacer (22). After the re-exposed metal (16) has been removed, a transistor is formed in which the metal layer (14,24) sets the work function of the gate of the transistor.
(FR) Une grille (18) de silicium polycristallin comportant des motifs est prévue sur une couche métallique (16), laquelle se situe sur une couche diélectrique (14) de grille, elle-même placée sur un substrat (12) semi-conducteur. Une couche mince (20) de matière est déposée sur la grille (18) de silicium polycristallin, et la couche métallique (16) exposée est ensuite attaquée afin de former un espaceur (22) de paroi latérale sur la grille (18) et d'exposer à nouveau la partie précédemment exposée de la couche métallique (16). La couche métallique (16) réexposée est attaquée à l'aide d'un agent d'attaque chimique sélectif par rapport à la matière diélectrique de grille et à l'espaceur (22). Même si l'attaque est sensiblement anisotrope, elle comporte un composant anisotrope qui attaquerait la paroi latérale de la grille (18) si celle-ci n'était pas protégée par l'espaceur (22). Après l'élimination du métal (16) réexposé, un transistor est formé, la couche métallique (12, 24) servant de grille du transistor.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)