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1. (WO2007001853) METHOD OF FORMING STACKED CAPACITOR DRAM CELLS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/001853 International Application No.: PCT/US2006/023116
Publication Date: 04.01.2007 International Filing Date: 12.06.2006
Chapter 2 Demand Filed: 24.01.2007
IPC:
H01L 21/02 (2006.01) ,H01L 21/8242 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way Boise, ID 83716, US (AllExceptUS)
Inventors:
JUENGLING, Werner; US
Agent:
LATWESEN, David, G.; Wells St. John P.S. 601 W. First Ave. Suite 1300 Spokane, WA 99201, US
Priority Data:
11/168,69927.06.2005US
Title (EN) METHOD OF FORMING STACKED CAPACITOR DRAM CELLS
(FR) CONSTRUCTIONS SEMI-CONDUCTRICES, CELLULES MEMOIRE, RESEAU DRAM, SYSTEMES ELECTRONIQUES, PROCEDES DE FORMATION DES CONSTRUCTIONS SEMI-CONDUCTRICES ET PROCEDES DE FORMATION DES RESEAUX DRAM
Abstract:
(EN) The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers being substantially orthogonal relative to first, second and third rows of contact plugs. An opening is etched which passes through each of the conductive layers within the plurality of conductive layers. The opening is disposed laterally between the first and second row of contact plugs. After etching the opening a dielectric material is deposited over the plurality of conductive layers and a second conductive material is deposited over the dielectric material. The invention includes an electronic system including a processor and a memory operably associated with the processor. The memory device has a memory array which includes double-pitched capacitors.
(FR) L'invention concerne une constructions semi-conductrice comprenant des rangées de fiches de contact et des rangées de plaques inférieures parallèles. Le pas des fiches est approximativement le double de celui des plaques. L'invention concerne également un procédé de formation d'une construction semi-conductrice. Une pluralité de couches conductrices est formée sur le substrat et est sensiblement orthogonale par rapport à des première, deuxième et troisième rangées de fiches de contact. Une ouverture est gravée et passe à travers chaque couche conductrice dans la pluralité de couches conductrices. L'ouverture est disposée de manière latérale entre les première et deuxième rangée de fiches de contact. Une fois l'ouverture gravée, un matériau diélectrique est déposé sur la pluralité de couches conductrices et un second matériau conducteur est déposé sur le matériau diélectrique. L'invention concerne également un système électronique comprenant un processeur et une mémoire associée de manière fonctionnelle au processeur. Le dispositif mémoire comprend un réseau mémoire présentant un condensateur à pas double.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080019068EP1920455JP2008547221CN101208775CN101826561