Processing

Please wait...

Settings

Settings

1. WO2007001783 - MIM CAPACITOR IN A SEMICONDUCTOR DEVICE AND METHOD THEREFOR

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

FCT/OSOB/BSBaor
Claims
What is claimed is:

1. A method for forming a semiconductor device having a planar metal-insulator-metal 5 (MIM) capacitor comprising:
providing a semiconductor substrate;
forming a first insulating layer over the semiconductor substrate;
planarizing the first insulating layer;
forming a second insulating layer over the first insulating layer;
0 forming a first plate electrode for the planar MIM capacitor over the second i insulating layer;
forming a third insulating layer over the first electrode; and
forming a second plate electrode for the planar MIM capacitor over the third
insulating layer.
5
2. The method of claim 1 , wherein planarizing the first insulating layer comprises
planarizing the first insulating layer using a chemical mechanical polishing process.

3. The method of claim 1, wherein the second plate electrode is electrically coupled to 0 an interconnect layer.

4. The method of claim 1 , wherein the first insulating comprises tetraethyl orthosilicate (TEOS).

5 5. The method of claim 1 , wherein the third insulating layer comprises a high K
dielectric formed to be between 20 to 1000 angstroms thick.

6. The method of claim 1, wherein the MIM capacitor is formed directly over a
conductor of an interconnect layer.
0
7. The method of claim 1 , wherein the MIM capacitor covers at least 50 percent of a
surface area of the semiconductor device.

P C "T, / U S O B / Ii!!! H Ei! S O
8. The method of claim 1 , further comprising forming an interconnect layer having a plurality of conductors over the third insulating layer.

9. The method of claim 8, wherein the interconnect layer is selected from a group
consisting of aluminum and copper.

10. A method for forming a semiconductor device having a metal-insulator-metal (MIM) capacitor comprising:
providing a semiconductor substrate;
forming an interconnect layer over the semiconductor substrate;
forming a first insulating layer over the interconnect layer;
planarizing the first insulating layer;
forming a second insulating layer over the first insulating layer;
forming a first plate electrode of the MIM capacitor over the second insulating
layer;
forming a third insulating layer over the first electrode; and
forming a second plate electrode of the MIM capacitor over the third
insulating layer.

11. The method of claim 10, wherein planarizing the first insulating layer comprises planarizing the first insulating layer using a chemical mechanical polishing process.

12. The method of claim 10, further comprising forming a second interconnect layer over the third insulating layer.

13. The method of claim 10, wherein the second plate electrode is electrically coupled to the second interconnect layer.

14. The method of claim 10, wherein the first insulating layer comprises tetraethyl
orthosilicate (TEOS).

15. The method of claim 10, wherein the third insulating layer comprises a high K
dielectric formed to be between 20 to 1000 angstroms thick.

16. The method of claim 10, wherein the MIM capacitor is formed directly over a
conductor of the interconnect layer.

17. The method of claim 10, wherein the MIM capacitor covers at least 50 percent of a surface area of the semiconductor device.

18. The method of claim 10, wherein the interconnect layer is selected from a group consisting of aluminum and copper.

19. A semiconductor device comprising:
a semiconductor substrate;
an interconnect layer formed over the semiconductor substrate;
a first planarized insulating layer formed over the interconnect layer;
a second insulating layer formed over the first insulating layer;
a first plate electrode formed over the second insulating layer;
a third insulating layer formed over the first electrode; and
a second plate electrode formed over the third insulating layer.

20. The semiconductor device of claim 19, wherein the first planarized insulating layer is planarized using a chemical mechanical polishing process.