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1. (WO2007001783) MIM CAPACITOR IN A SEMICONDUCTOR DEVICE AND METHOD THEREFOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/001783 International Application No.: PCT/US2006/022280
Publication Date: 04.01.2007 International Filing Date: 08.06.2006
IPC:
H01L 21/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Applicants:
FREESCALE SEMICONDUCTOR [US/US]; 6501 William Cannon Drive West Austin, TX 78735, US (AllExceptUS)
ROBERTS, Douglas, R. [US/US]; US (UsOnly)
HUFFMAN, Gary, L. [US/US]; US (UsOnly)
Inventors:
ROBERTS, Douglas, R.; US
HUFFMAN, Gary, L.; US
Agent:
KING, Robert, L. ; 7700 W. Parmer Lane, MD:PL02 Austin, Texas 7877, US
Priority Data:
11/168,57928.06.2005US
Title (EN) MIM CAPACITOR IN A SEMICONDUCTOR DEVICE AND METHOD THEREFOR
(FR) CONDENSATEUR MIM DANS UN DISPOSITIF SEMI-CONDUCTEUR ET PROCEDE ASSOCIE
Abstract:
(EN) A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device (10). The capacitor has a lower plate electrode (36) and an upper plate electrode (40). An insulator (38) is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer (28) is deposited over the metal of an interconnect layer. The first insulating layer (28) is planarized using a chemical mechanical polish (CMP) process. A second insulating layer (32) is then deposited over the planarized first insulating layer. The first plate electrode (36) is formed over the second insulating layer (32). An insulator (38) is formed over the first plate electrode and functions as the capacitor dielectric. A second plate electrode (40) is formed over the insulator (39). Planarizing the first insulating layer and depositing a second insulating layer over the first insulating layer, reduces defects and produces a more reliable capacitor.
(FR) La présente invention concerne un condensateur MIM établi sur une ou plusieurs couches d'interconnexion métalliques dans un dispositif semi-conducteur (10). Le condensateur présente une électrode en plaque inférieure (36) et une électrode en plaque supérieure (40). Un isolant (38) est formé entre les électrodes en plaque. Avant de produire la première électrode en plaque, une première couche isolante (28) est déposée sur le métal d'une couche d'interconnexion. La première couche isolante (28) est planarisée au moyen d'un processus de polissage chimico-mécanique (CMP). Une seconde couche isolante (32) est ensuite déposée sur la première couche isolante planarisée. La première électrode en plaque (36) est formée sur la seconde couche isolante (32). Un isolant (38) est formé sur la première électrode en plaque (32) et sert de diélectrique de condensateur. Une seconde électrode en plaque (40) est formée sur l'isolant (39). Il est possible de réduire le nombre de défauts et de produire un condensateur plus fiable en planarisant la première couche isolante et en déposant une seconde couche isolante sur cette première couche isolante.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN101213641