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1. (WO2007001782) TUNABLE ANTIFUSE ELEMENT AND METHOD OF MANUFACTURE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/001782 International Application No.: PCT/US2006/022278
Publication Date: 04.01.2007 International Filing Date: 08.06.2006
IPC:
H01L 21/82 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 21/44 (2006.01) ,H01L 21/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
44
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
Applicants:
FREESCALE SEMICONDUCTOR [US/US]; 6501 William Cannon Drive West Austin, TX 78735, US (AllExceptUS)
PARRIS, Patrice, M. [GY/US]; US (UsOnly)
CHEN, Weize [CN/US]; US (UsOnly)
MCKENNA, John, M. [US/US]; US
MORRISON, Jennifer, H. [US/US]; US (UsOnly)
DE SOUZA, Richard, J. [IN/US]; US (UsOnly)
Inventors:
PARRIS, Patrice, M.; US
CHEN, Weize; US
MCKENNA, John, M.; US
MORRISON, Jennifer, H.; US
DE SOUZA, Richard, J.; US
Agent:
KING, Robert, L. ; 7700 W. Parmer Lane, Md:pl02 Austin, TX 78729, US
Priority Data:
11/169,96228.06.2005US
Title (EN) TUNABLE ANTIFUSE ELEMENT AND METHOD OF MANUFACTURE
(FR) ELEMENT ANTIFUSIBLE ACCORDABLE ET PROCEDE POUR LE PRODUIRE
Abstract:
(EN) A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
(FR) La présente invention concerne un élément antifusible accordable (102, 202, 204, 504, 952) et un procédé pour le fabriquer. Cet élément comprend une matière de substrat (101) qui présente une zone active (106) formée dans une surface, une électrode de grille (104) qui présente au moins une partie placée au-dessus de la zone active (106), ainsi qu'une couche diélectrique (110) qui est placée entre l'électrode de grille (104) et la zone active (106). La couche diélectrique (110) implique la fabrication d'une structure à gradins accordable (127). En service, une tension appliquée entre l'électrode de grille (104) et la zone active (106) créé une voie de courant à travers la couche diélectrique (110) et une rupture de la couche diélectrique (110) dans plusieurs régions de rupture (130). La couche diélectrique (110) peut être accordée en faisant varier les épaisseurs de couches en gradins et la géométrie de la couche.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)