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1. (WO2007001617) METHOD OF MAKING A SUBSTRATE CON TACT FOR A CAPPED MEMS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/001617 International Application No.: PCT/US2006/016265
Publication Date: 04.01.2007 International Filing Date: 28.04.2006
IPC:
H01L 21/00 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/4763 (2006.01) ,H01L 21/44 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
46
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428142
461
to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
4763
Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
44
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428158
Applicants:
FREESCALE SEMICONDUCTOR, INC. [US/US]; 3501 West William Cannon Drive Austin, Texas 78735, US (AllExceptUS)
SALIAN, Arvind, S. [IN/US]; US (UsOnly)
DESAI, Hemant, D. [US/US]; US (UsOnly)
HOOPER, Stephen, R. [US/US]; US (UsOnly)
MCDONALD, William, G. [US/US]; US (UsOnly)
Inventors:
SALIAN, Arvind, S.; US
DESAI, Hemant, D.; US
HOOPER, Stephen, R.; US
MCDONALD, William, G.; US
Agent:
KING, Robert, L. ; 7700 W. Parmer Lane, MD:PL02 Austin, Texas 78729, US
Priority Data:
11/158,79521.06.2005US
Title (EN) METHOD OF MAKING A SUBSTRATE CON TACT FOR A CAPPED MEMS
(FR) PROCÉDÉ DE FABRICATION D'UN CONTACT DE SUBSTRAT POUR UN MEMS PROTÉGÉ AU NIVEAU DU BOÎTIER
Abstract:
(EN) Methods have been provided for forming a micro-electromechanical systems ('MEMS') device (100) from a substrate (500) comprising a handle layer (108) and a cap (132) overlying the handle layer (108). In one exemplary embodiment, the method includes cutting through the substrate (500) to separate the substrate (500) into a first die (148) and a second die (150), the first die (148) having a first sidewall (138), and depositing a conductive material (182) onto the first sidewall (138) to electrically couple the cap (132) to the handle layer (108).
(FR) La présente invention concerne un procédé de fabrication d'un dispositif de microsystèmes électromécaniques (« MEMS ») (100) à partir d'un substrat (500) comprenant une couche d'espacement (108) et un couvercle (132) recouvrant la couche d'espacement (108). Dans un mode de réalisation exemplaire, le procédé comprend le découpage à travers le substrat (500) pour séparer le substrat (500) en une première puce (148) et en une seconde puce (150), la première puce (148) comportant une première paroi latérale (138), et la déposition sur la première paroi latérale (138) d'un matériau conducteur (182) pour coupler électriquement le couvercle (132) à la couche d'espacement (108).
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
JP2008543594US20060286706CN101553899