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1. (WO2007000695) PACKAGE, SUBASSEMBLY AND METHODS OF MANUFACTURING THEREOF
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/000695 International Application No.: PCT/IB2006/052034
Publication Date: 04.01.2007 International Filing Date: 22.06.2006
IPC:
H01L 23/36 (2006.01) ,H01L 21/68 (2006.01) ,H01L 21/48 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
68
for positioning, orientation or alignment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
Applicants:
KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL (AllExceptUS)
DEKKER, Ronald [NL/NL]; NL (UsOnly)
MICHIELSEN, Theodorus, M. [NL/NL]; NL (UsOnly)
MEIJER, Eduard, J. [NL/NL]; NL (UsOnly)
Inventors:
DEKKER, Ronald; NL
MICHIELSEN, Theodorus, M.; NL
MEIJER, Eduard, J.; NL
Agent:
NOLLEN, Maarten, D-J.; Prof. Holstlaan 6 NL-5656 AA Eindhoven, NL
Priority Data:
05105830.329.06.2005EP
Title (EN) PACKAGE, SUBASSEMBLY AND METHODS OF MANUFACTURING THEREOF
(FR) BOITIER, SOUS-ENSEMBLE ET PROCEDE DE FABRICATION CORRESPONDANT
Abstract:
(EN) The package (100) of the invention comprises at least one semiconductor device (30) provided with bond pads (32); an encapsulation (40), an interconnect element (20) and a heatsink (90). This element comprises a system of electrical interconnects (12) and is at least substantially covered by a thermally conductive, electrically insulating layer (11) at a first side (1) and that is provided with an electric isolation (13) at a second side (2), such that the isolation (13) and the thermally conducting layer (11) electrically isolate the electrical interconnects (12) from each other. At least one component of the encapsulation (40) and the heatsink (90) has an interface with the interconnect element (20), which interlace extends over substantially the complete side (1,2) to which the said component (40,90) is attached.
(FR) La présente invention concerne un boîtier (100) comprenant au moins un dispositif à semi-conducteur (30) pourvu de plots de contact (32), d'une inclusion (40), d'un élément d'interconnexion (20) et d'un puits thermique (90). Cet élément, qui comprend un système d'interconnexions électrique (12) est sensiblement recouvert d'un premier côté (1) d'une couche (11) électriquement isolante et thermoconductrice, et garnie d'une isolation électrique (13) de l'autre côté (2), de façon que l'isolation (13) et la couche thermoconductrice (11à isole électriquement l'une de l'autre les interconnexions électriques (12). L'un des composants au moins de l'inclusion (40) et du puits thermique (90) comporte une interface avec l'élément d'interconnexion (20), laquelle interface vient sensiblement au-dessus de la totalité du côte (1, 2) auquel tient ledit composant (40, 90).
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1900023JP2008545263US20090127702CN101213661BRPI0612113MYPI 20063051
IN6063/CHENP/2007