Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2007000690) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/000690 International Application No.: PCT/IB2006/052013
Publication Date: 04.01.2007 International Filing Date: 21.06.2006
IPC:
H01L 29/786 (2006.01) ,H01L 27/06 (2006.01) ,H01L 29/423 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants:
NXP B.V. [NL/NL]; High Tech Campus 60 NL-5656 AG Eindhoven, NL (AllExceptUS)
SONSKY, Jan [CZ/BE]; NL (UsOnly)
MEUNIER-BEILLARD, Philippe [FR/BE]; NL (UsOnly)
VAN DALEN, Rob [NL/NL]; NL (UsOnly)
WILLEMSEN, Marnix, B. [NL/NL]; NL (UsOnly)
Inventors:
SONSKY, Jan; NL
MEUNIER-BEILLARD, Philippe; NL
VAN DALEN, Rob; NL
WILLEMSEN, Marnix, B.; NL
Agent:
PENNINGS, Johannes; NXP Semiconductors IP Department High Tech Campus 60 NL-5656 AG Eindhoven, NL
Priority Data:
05105719.827.06.2005EP
Title (EN) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD
(FR) PROCEDE DE FABRICATION D'UN DISPOSITIF A SEMI-CONDUCTEURS ET DISPOSITIF A SEMI-CONDUCTEURS OBTENU SELON CE PROCEDE
Abstract:
(EN) Method of manufacturing a semiconductor device and semiconductor device obtained with such a method. The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which is provided with at least one semiconductor element, wherein in the semiconductor body (12) a semiconductor region (1) of a material comprising a mixed crystal of silicon and another group IV element is formed which semiconductor region (1,111) is buried by a silicon layer (2). According to the invention on a surface of the semiconductor body (12) a mask (3) comprising an opening (4) is provided, the semiconductor region (1,111) of the material comprising a mixed crystal of silicon and another group IV element is selectively deposited in the opening (4,44), the mask (3,33) is at least partly removed, and subsequently the silicon layer (2) is deposited uniformly on the surface of the semiconductor body (12). In this way various high-quality devices can be obtained. The semiconductor region (1,111) preferably comprises SiGe and may form part of the device (10) or may be sacrificed in order to form an insulating or conducting region in the device (10).
(FR) L'invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs et un dispositif à semi-conducteurs obtenu selon ce procédé. L'invention concerne également un procédé de fabrication d'un dispositif à semi-conducteurs (10) qui comprend un substrat (11) et un corps semi-conducteur (12) de silicium pourvu d'au moins un autre élément semi-conducteur. Une région semi-conductrice (1) composée d'un matériau comprenant un cristal de silicium mélangé et un autre élément du groupe IV est formée dans le corps semi-conducteur (12). Cette région (1, 111) est recouverte par une couche de silicium (2). Selon l'invention, un masque (3) est formé sur une surface du corps semi-conducteur (12), ce masque comprenant une ouverture. La région semi-conductrice (1, 111) du matériau comprenant un cristal de silicium mélangé et un autre élément du groupe IV est sélectivement déposée dans l'ouverture (4, 44) ; le masque (3, 33) est au moins partiellement éliminé ; et la couche de silicium (2) est ensuite déposée uniformément sur la surface du corps semi-conducteur (12). Divers dispositifs de haute qualité peuvent être ainsi obtenus. La région semi-conductrice (1, 111) comprend de préférence du SiGe et peut faire partie du dispositif (10) ou être sacrifiée de façon à former une région isolante ou conductrice dans le dispositif (10).
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1900037JP2008544563CN101208804